Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 63 3. Enter the following information in the table: Name value PCIE HSIF and Interface name PCIE HSIF Note: The Mapping table Name and Interface need to match the interface name in the Object and ObjectRule tables. Update the other information in the header as required. 4. Define information in the Data rows as follows: Header: Type Alias Design Data: * HSIF_ X HSIF_RX:HSIF_ TX * HSIF_ RX HSIF_RX * HSIF_T X HSIF_TX * LANE <{0-7}> 5. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 6. Open the starter Object table in the Lab-7_Viper_ASIC_to_Virtex-7 folder: object_grouping_PCIe_HSIF.xlsx 7. Enter the following information in the table: Object name VIPER_TO_VIRTEX-7 and Interface name PCIE HSIF Update the other information in the header as required.