Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 59 Rule column: i. PhysicalCSet:85_OHM_DP is an existing Physical Constraint Set that already exists in the design to drive Diff Pair rules. ii. DP_PHASE is the Rule Specification to drive Electrical rules. 9. Save the changes and then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 10. Open the starter Object Rule table in the Lab-6_Viper_ASIC_to_PCIe_INT folder: objectrule_class_to_class_PCI_Express.xlsx 11. Enter the following information in the table: ObjectRule name VIPER_TO_PCIE and Interface name PCIE INT Update the other information in the header as required. 12. Define information in the Header and Data rows: Header: Type=Intra- Group Type=PCI_RX Type Rule Spacing Rule Spacing Rule Data: PCI_TX SPC:15MIL_SPA CE SPC:5MIL_SPA CE SPC:10MIL_SPA CE Type column specifies the Type classification for TX Nets in the Object table. Rule column specifies the Rule Specification and Rule Set to drive Spacing rules between Type PCI_TX groups to all nets in the design. Type=Intra-Group specifies the Rule Specification and Rule Set to drive Spacing rules within the Type PCI_TX groups. Type= PCI_RX specifies the Type classification for the RX Nets defined in the Object table. The Rule Specification and Rule Set specified in this column drive Spacing rules to Type PCI_TX groups.