Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 44 6. Open the starter Object Rule table in the Lab-3_DSP_to_HS_CONN folder: objectrule_class_to_class_EMIFA.xlsx 7. Enter the following information in the table: ObjectRule name DSP_TO_CONN and Interface name EMIFA Update the other information in the header as required. 8. Define information in the Header and Data rows: Type=Intra- Group Type=ADDR Type=MEM_MA P Type=BYTE_EN Type Rule Spacing Rule Spacing Rule Spacing Rule Spacing Rule DAT A SPC:15MIL_SP ACE SPC:5MIL_SPA CE SPC:10MIL_SP ACE SPC:10MIL_SP ACE SPC:10MIL_SP ACE Type column specifies the Type classification for Data Bus in the Object table. Rule column specifies the Rule Specification and Rule Set to drive Spacing rules between Type DATA groups to all nets in the design. Type=Intra-Group specifies the Rule Specification and Rule Set to drive Spacing rules within the Type DATA groups. Type= specifies the Type classification defined in the Object table. The Rule Specification and Rule Set specified in this column drive Spacing rules to Type DATA groups. 9. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 10. Open Constraint Manager and select Tools > Constraint Compiler. 11. Expand the acc_library folder; then select the folders Lab- 1_Rule_Spec_Sets and Lab-3_DSP_to_HS_CONN.

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
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