Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 5 Overview Various manufacturers provide EDA design guides to ensure their customers leverage their technology to its fullest extent and develop products that perform as expected. These design guides are normally interface specific, and it is left up to the designer to interpret guidelines to apply appropriate rules in the layout tool. Many times, these rules are not necessarily understood, which leads to under or over constraining the design. Manufacturers sometimes provide reference designs and design review services to help customers achieve the best results for their products, but this can increase the design schedule considerably, which could impact the overall product schedule. This workshop introduces ACC, an infrastructure to support automatic translation of design constraints from an external source directly into Constraint Manager. The compiler is used to seed initial constraint information in the design or update a design that has existing constraints. At the simplest level, ACC will use the design's connectivity (buses, Differential Pairs, nets, etc.) in conjunction with "data agnostic" constraint information to create specific rules for various interfaces in the design. Benefits of ACC "Single source" reuse path from design to design for consistent constraint entry, without going through the Export/Import DCFX/TCFX process Facilitates the automatic generation of constraint containers (Diff Pairs, Net Classes, Net Groups, Match Groups, and expanded Constraint Rule Sets) "One-to-many" constraint explosion to propagate rules down to the lowest level generating all supporting objects and groups avoiding manual efforts