Allegro PCB Designer RAKs

Allegro Constraint Compiler

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Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 40 4. Define the following rules in the columns: Header: MIN_LINE_WIDT H MAX_LINE_WID TH MIN_NECK_WID TH MAXIMUM_NECK_LEN GTH Data: 10 10 6 100 Header: LINE_TO_LINE_SPAC ING LINE_TO_THRUVIA_SPA CING LINE_TO_SHAPE_SPA CING Data: 8 8 10 Header: TOTAL_ETCH_LENGTH _MAX Data: 2000 5. Save the changes; then select File > Save As to save the spreadsheet in CSV format under the same filename using the file type CSV (Comma delimited) (.csv). 6. Open the starter Object table in the Lab-2_Virtex-5_to_Virtex-7 folder: object_grouping_Protocol_Analyzer.xlsx 7. Enter the following information in the table: Object name VIRTEX-5_TO_VIRTEX-7 and Interface name PPC_A Update the other information in the header as required. 8. Define information in the Data row: Header: Group Name Nets Type Rule Count Data: NetGroup PPC_ A PPC_A<{0- 31}> PPC_A_RUL ES 32 Nets column: i. PPC_A<{0-31}> selects 32 nets using a Number Range {...}. (PPC_A<0>, PPC_A<1>, PPC_A<2>, PPC_A<3>, PPC_A<4>, … PPC_A<31>) Rule column calls out the Rule Specification created in Step 4 of this lab.

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