Allegro PCB Designer RAKs

Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 26 Object Rule Table (Class-to-Class Rules) Example: ObjectRul e MY_CLA SS Revision 1 Created by Cadence Header Type=Intra- Group Type=BYTE Type=ADDR Type Rule Spacing Rule Spacing Rule Spacing Rule Data BYTE HS_SPACE:30 MIL HS_SPACE:6MI L HS_SPACE:HS_15 MIL HS_SPACE:25 MIL End Results: Spacing for the group of nets in Type BYTE will be checked with respect to all other Nets using Rule Set 30MIL from the HS_SPACE Rule Specification. Spacing for nets contained in Type BYTE (Intra-Group) will be checked with respect to each other using Rule Set 6MIL from the HS_SPACE Rule Specification. Spacing for a group in Type BYTE will be checked with respect to other Type BYTE groups using Rule Set 15MIL from the HS_SPACE Rule Specification. Spacing for each group in Type BYTE will be checked with respect to Type ADDR groups using Rule Set 25MIL from the HS_SPACE Rule Specification. Rule columns could also reference existing CSets SpacingCSet:. Type designations will result in a Spacing Net Class with an "NC_" prefix in Layout using the group name defined in the Object table.

• Cover
• Purpose
• Audience
• Terms
• Overview
• Benefits of ACC
• Functional Overview
• Table and Specification Format Overview
• Mapping Name Table
• Object Table
• Rule Specification Table (Rule Sets)
• Object Rule Table (Object Rules)
• Object Rule Table (Class-to-Class Rules)
• User Interface and Data Query
• Validation and Apply Constraints to Design
• Reporting
• ACC Lab Exercises
• License Requirements / Workshop Structure
• Lab 1-1: Rule Specifications Structure Review
• Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1)
• Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4)
• Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2)
• Lab 1-5: VIRTEX-7 (RefDes U1) To PCIe HSIO (RefDes J3)
• Lab 1-6: Viper (RefDes U34) To PCIe CONN (RefDes J1)
• Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional
• Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)
• Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)
• Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35)
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