Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 3 Contents Purpose...................................................................................................................................... 4 Audience .................................................................................................................................... 4 Terms ......................................................................................................................................... 4 Overview .................................................................................................................................... 5 Benefits of ACC .................................................................................................................... 5 Functional Overview ............................................................................................................ 6 Table and Specification Format Overview ....................................................................... 8 Mapping Name Table ........................................................................................................ 12 Object Table ............................................................................................................................ 14 Rule Specification Table (Rule Sets) .............................................................................. 17 Object Rule Table (Object Rules) .................................................................................... 22 Object Rule Table (Class-to-Class Rules) ..................................................................... 25 User Interface and Data Query ........................................................................................ 27 Validation and Apply Constraints to Design ................................................................... 33 Reporti ng ............................................................................................................................. 34 ACC Lab Exercises ................................................................................................................ 35 License Requirements / Workshop Structure ................................................................ 35 Lab 1-1: Rule Specifications Structure Review ............................................................. 36 Lab 1-2: VIRTEX-5 (RefDes U3) To VIRTEX-7 (RefDes U1) ..................................... 39 Lab 1-3: DSP (RefDes U2) To HS Connector (RefDes U4) ........................................ 42 Lab 1-4: VIRTEX-7 (RefDes U1) To DSP (RefDes U2) ............................................... 46 Lab 1-5: VIRTEX-7 (RefDes U1) To PC Ie HSIO (RefDes J3) .................................... 50 Lab 1-6: Viper (RefDes U34) To PC Ie CONN (RefDes J1) ......................................... 56 Lab 1-7: Viper (RefDes U34) To Virtex-7 (RefDes U1) – Optional............................. 62 Lab 1-8: Viper (RefDes U34) To SATA Connectors (RefDes J2,J7-9,J11,J12)....... 68 Lab 1-9: VIRTEX-7 (RefDes U1) to DDR3 Connector (RefDes XP1)........................ 74 Lab 1-10: Viper (RefDes U34) To On-Board DDR3 (RefDes U9, U12, U26-30, U35) ............................................................................................................................................... 79 Support..................................................................................................................................... 82 Feedback ................................................................................................................................. 82