Allegro Constraint Compiler: Workshop
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Column Header Descriptions
Type
Design object type to be processed (Part, Net, "*" means all object types)
Alias
Name for design objects referenced in other tables
Design
Design object to be mapped using Explicit Name, Regular Expression, or Number
Range { - }
Mapping Name Table Example:
Name MY_MAP
Revision 1
Created by
Cadenc
e
Header Type Alias Design
Alias referenced and expanded in
tables
Data
Part PROC U25
${PROC} -> U25
Part MEM U{1-5}
${MEM} -> U1, U2, U3, U4, U5
Part FLASH U10:U14:U28:U35
${FLASH} -> U10, U14, U28, U35
Net
DDR_D
Q
DDR_DQ<{0-3}>
${DDR_DQ} -> DDR_DQ<0>,
DDR_DQ<1>, DDR_DQ<2>,
DDR_DQ<3>
Net
PCIE_H
S
HS[O,I]_{0-3}
${PCIE_HS} -> HSO_0, HSO_1,
HSO_2, HSO_3, HSI_0, HSI_1, HSI_2,
HSI_3
Net
PCIE_D
P
HS[O,I]_[N,P](0)
${PCIE_DP} -> HSO_N0, HSO_P0,
HSI_N0, HSI_P0
* BANK M{0-3}
DDR_${BANK} -> DDR_M0, DDR_M1,
DDR_M2, DDR_M3
* LANE BYTELANE{0-8}
DDR_${LANE} -> DDR_BYTELANE0,
DDR_BYTELANE1,
DDR_BYTELANE2,
DDR_BYTELANE3,
DDR_BYTELANE4,
DDR_BYTELANE5,
DDR_BYTELANE6,
DDR_BYTELANE7, DDR_BYTELANE8
End
Note: First column section text marks the beginning of each section of the template
until another section text mark is seen. (Header, Data, and End)
