Issue link: https://resources.pcb.cadence.com/i/1180070
Allegro Constraint Compiler: Workshop Learn more at Cadence Support Portal - https://support.cadence.com © 2019 Cadence Design Systems, Inc. All rights reserved w orldw ide. Page 12 Mapping information could also be stored in a Global Name table. Here is an example of nets in the design and its associated mapping for the Object table. Nets: PCIE_RXN<7:0>, PCIE_RXP<7:0>, PCIE_TXN<7:0>, PCIE_TXP<7:0> Name PCI Revision 1 Interface PCI Created by Cadence Header Type Alias Design Data * PCIE PCIE_RX:PCIE_TX * LANE {0-7} End Object PCI_OBJECTS Revision 1 Interface PCI Units mil Created by Cadence Header Group Name Nets Count Data DiffPair ${PCIE}<${LANE}> ${PCIE}[N,P]<${LANE}> 2 NetGroup ${PCIE} ${PCIE}[N,P]<${LANE}> 16 End Results: Diff Pairs DP_PCIE_RX<7:0> and DP_PCIE_TX<7:0> Net Groups NG_PCI_RX with eight Diff Pair members (DP_PCIE_RX<7:0>) Net Groups NG_PCI_TX with eight Diff Pair members (DP_PCIE_TX<7:0>) Mapping Name Table When running the compiler, the software will leverage this table to map alias placeholders referenced in the constraints data tables to be replaced with design- specific names. This is beneficial to keep a large part of the constraints data reusable from design to design and provide a central location to remap the alias over to the design-specific name.