Verification

© 2019 Cadence Design Systems, Inc. All rights reserved. Multi-Level Abstraction RTL Level Software Level Transistor Level Gate Level Cycles per $ per Day Raw Performance Performance Optimization Scalable Architecture Bare Metal Compute Bugs per $ per Day Smart Bug Hunting Debug Coverage & Metrics Formal and Lint Portable Stimulus VIP Cadence Verification Mission: Verification Throughput

• Optimizing Verification Throughput in a Connected World of 5G and ML/AI
• Challenges & Opportunities in Electronics Innovation
• Cadence Intelligent System Design
• A Data-driven World
• Datacenter ChallengesWorkload-optimized, high-performance compute, connectivity, accelerators – AI/ML/DL
• Machine Learning / Artificial Intelligence - ChallengesTraining, Inferencing and Specialized IP
• The Promise of 5G – Where to Start?
• 5G — New Bandwidth, New Subsystems
• 5G Ecosystem Opportunities and Requirements 1/2
• 5G Ecosystem Opportunities and Requirements 1/2 (1)
• Design Start Market: Bifurcation
• The Unifying Challenge: Verification and Software
• So How Do You Win a Race?
• Slide Number 14
• Slide Number 15
• Slide Number 16
• The Verification Race!
• Cadence Verification Mission
• Cadence Verification Mission: Verification Throughput
• Raw Performance
• Bare Metal Compute
• Xcelium next-generation high performance simulator
• Multi-Core and Simulation Regressions
• Slide Number 24
• The Verification Productivity Loop
• Emulation and Prototyping!
• Unified Frontend for Emulation and Prototyping
• Palladium Emulation AND Protium Prototyping
• Unified Flow for Emulation and Prototyping(Source: Toshiba, CDN-Live 2019)
• Hardware Portfolio - Now with Multi-MHz @ BG
• New: Protium X1 Enterprise Prototyping System
• Scalable Bare Metal Compute – Users & Capacity
• Multi-Level Abstraction
• Users Care About Many, Often Conflicting Requirements
• Slide Number 35
• Wouldn't it Be Nice if "One Tool Would Rule Them All"?
• A Continuum of Dynamic EnginesVerification and software platforms need to interoperate
• Hardware/Software Co-Verification during SoC Design
• Multi-Level Abstraction
• Virtualization with Emulation Enables SW Shift-LeftUsing virtual platforms and hybrids to accelerate SW development and HW/SW validation
• IP and SoC Hybrid Examples
• Cadence Virtual/Hybrid Prototyping Environment
• More Robust Hardware and Software!Greatly accelerated Time-to-Market!
• Smart Bug Hunting – Putting It All Together
• VIP Catalog - Latest Protocols Support
• Perspec Standardization, Recognition, and Multi-Vendor Support
• vManager: Verification Predictability, Productivity, QualityWith better automation
• Indago Debug
• ML-enabled Smart JasperGoldThird-generation JasperGold formal verification platform
• Smart Bug Hunting Leadership
• Summary … What's Next?
• Cadence Verification Mission: Verification Throughput (1)
• Cadence Leadership in Machine Learning
• And then there are Digital Twins …
• Data-Transfer for Digital Twins
• Completely New Verification Challenges Ahead!
• Strategic Partnership with Green Hills Software
• Strong Verification Partnerships
• The Cadence Verification Suite
• Cadence Intelligent System Design (1)
• Slide Number 61