Issue link: https://resources.pcb.cadence.com/i/1149719
© 2019 Cadence Design Systems, Inc. All rights reserved. A Continuum of Dynamic Engines Verification and software platforms need to interoperate SDK OS Simulation Highest speed Earliest in flow Ignores HW Easy replication Cross-compile Virtual Platform Almost @ speed Pre-RTL Less accurate TLM HW Debug Great SW debug Easy replication Less HW detail Slower with detail HDL Simulation KHz Range Early RTL Golden Reference Best HW debug Limited SW Debug Easy replication Mixed-abstractions Slow SW execution Acceleration Emulation MHz Range Early RTL Min RTL mods Detailed HW debug Great SW Debug Harder to replicate Datacenter access Contested Resource FPGA Prototype 10's of MHz Later RTL Some RTL mods Some HW debug Great SW Debug OK to replicate Harder Bring-up Prototyping Board Real time speed Fully accurate Actual Silicon Difficult HW debug OK SW Debug Easy to replicate HW changes hard