Issue link: https://resources.pcb.cadence.com/i/1149719
© 2019 Cadence Design Systems, Inc. All rights reserved. Virtualization with Emulation Enables SW Shift-Left Using virtual platforms and hybrids to accelerate SW development and HW/SW validation All RTL, Silicon Final HW/SW Validation All Virtual Pre-RTL SW Development SoC Virtual Platform OS SoC Drivers Tests and Benchmarks IP RTL IP Hybrid Pre-SoC IP / Driver Validation & Optimization RTL – Palladium or Xcelium RTL Memory CPU Virtual Platform OS IP Driver RTL IP Tests and Benchmarks SoC RTL SOC Hybrid Pre-Tapeout HW/SW Validation DDR3 Display INTC Timer CSI DSI UART GPU MC SATA USB3 … System Boot USB2 Ethernet MMP IP 2 CPU Virtual Platform OS SoC Drivers Tests and Benchmarks OS SoC Drivers Tests and Benchmarks Design Flow Shift Left Virtual Models - VSP SW stack RTL Models - Color Code DDR3 Display INTC Timer CSI DSI UART GPU MC SATA USB3 … System Boot USB2 Ethernet Mem IP 2 CPU CPU Emulation, FPGA Proto Pre-Tapeout Fully Accurate HW/SW Validation SoC RTL OS SoC Drivers Tests and Benchmarks DDR3 Display INTC Timer CSI DSI UART GPU MC SATA USB3 … System Boot USB2 Ethernet Mem IP 2 CPU CPU