Verification

Verification Futures

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© 2019 Cadence Design Systems, Inc. All rights reserved. Cadence Virtual/Hybrid Prototyping Environment Virtual and Hybrid platform and SW Bring-Up Services TLM Libraries 3 rd Party Debuggers Platform Assembly Create, integrate, Extend Run Time Environment Heterogenous, multi- process, multi-system IEEE 1666 SystemC Engine based on Xcelium Native Debug SystemC, SW SimVision Hybrid Connections to RTL Engines Xcelium, Palladium Z1, Protium External IF Virtual Device Models Base Libraries Modeling Automation Processors Peripherals Interconnect Open & Standard's based Common Components Peripheral Models Connected to Platform Built in TLM Debug Low Level SW Debug Software Debug Create Platform Use Platform for Software Development Smart Memory, Transactors

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