Micro-Vias - An Answer to the High-Density Blues

John Burkhert

It’s almost inevitable that a component that works well and lasts a long time will eventually be put on a list of parts that you should not specify for mass production. Newer, better parts are on the way. The thinking goes that the micro controllers and other devices on your board are already fine-pitch so you can accommodate another one. That’s how we end up with those five-pin regulators with a tiny diamond shaped pin trapped between four bevelled rectangles.

Figure 1. Image Credit: Author - There are many component types that assume HDI technology will be used as a matter of course.

Advantage: Component to Component Spacing

The via-in-pad trick enables the high component density by enabling routing that is 100% internal to the board with no exposed traces. The space that is normally set aside for the fan-out via can be used for the next component with the following stipulations.

Test access is maintained
Rework clearance - Desoldering
Electrical Isolation - Shielding
Thermal considerations - Heat sink, heat pipe
Mechanical interference - Headroom
The pick & place accuracy

Within the above parameters, placement can be as tight as a jigsaw puzzle. Placement of discrete SMD components can get very cosy. When it comes to the smallest chip caps and resistors, a solder dam between their respective pads is sufficient space. This assumes that the body of the part resides within the limits of the pads as is typical of the micro-caps. I normally recommend a soldermask dam with a minimum width of 100 microns (4 mils). That said, 75 microns is the new 100 as far as trends go among the fab houses putting down a solder dam.

An ancillary benefit of the via-in-pad method is that we shorten up the inductive loops of the decoupling capacitors as we skip the fan-out segments. Intuitively, the placement of the cap should create a bridge between a power pin and a local ground pin. In some applications, the exact pin-pair matters. Even if that information is in the relevant app-notes, it is helpful to capture those types of provisions on the schematic diagram.

The Most Basic Application of Micro-Vias

Setting the way-back machine to Y2K, the company I was working for was blazing a trail with a device package like a QFN (quad flat-pack no-lead) except that it had two rings of pins around the central ground paddle instead of the usual one ring. They weren’t really pins either, more like bumps and were spaced at 0.5 mm with square pads all around.

The only escape for that inner ring was to use laser technology to form the holes from the surface copper to the layer below. The hole can be as small as you like but the need for plating the resulting hole is the limiting factor. What works best is a hole that is wider than it is deep. The width-to-depth aspect ratio is the key to reliable plating. We want a hole with more width than depth.

Figure 2. Image Credit: Author - Micro-vias can be used as necessary to get a good ground connection under hard working parts.

As an aside, the technology roadmaps are pointing towards a one-to-one ratio somewhere in the future but right now, a 0.6:1 ratio is mainstream enough to use with confidence. Meanwhile, the size of the SMD pad for the device was 300 microns so that was the designated via size. The problem we’re trying to solve allows for a finished hole size of 100 microns when you allow for tolerance build-up.

Disadvantage: Locked Into Thin Dielectric Materials

The end result is that the maximum dielectric thickness we could use is 60 microns due to the aspect ratio mentioned above. Note that the thin prepreg materials are always in demand for the sequential build-up process. Writing paper is around 100 microns in thickness. This material is half of that and is integral to the whole HDI technology solution.

A four-layer board using micro-vias is going to have a thick middle layer between layers two and three just to have enough backbone rigidity. This leaves an asymmetric faraday cage where layer 2 routing is closer to layer 1 than to layer 3. The better impedance calculators will have an option for this type of inner-layer routing.

The downside here is that trace impedance is a function of the dielectric thickness. A rule of thumb you can use is that a 50 ohm line width correlates with the dielectric thickness. The trace width is about the same as the thickness of the dielectric. The dielectric constant, copper thickness and the presence of soldermask all play a part in the actual impedance calculations. It would be an elite vendor who could produce line widths in this range, especially on the outer layers.

Getting away from those lossy 60 micron lines can be achieved by creating voids in the layer immediately below the transmission line. Then, a top-layer trace would use layer 3 for a reference plane. Observing the not-unusual-for-analog idea of making the trace width match pad size, the reference plane can be as far down as you like. This advice is mainly about the type of trace that you would only route on an outer layer in the first place. Designing RF amplifiers is a thing unto itself.

The Micro-Via as a Thermal Path

One of the best uses of the micro-via from the outer layer to the first inner layer is in the middle of a quad-flat-pack type of package where there is a big ground pin in the center of the package. It doesn’t require much special handling to implement the via-in-pad technology. The surface finish should be upgraded to electroless nickel/immersion gold (ENIG) to get flatter SMT pads that give better yields in assembly.

Adding vias to SMT pins should not alter the geometry of the original pin. Completely inside or outside of the pad rather than straddling the edge will make soldering more consistent. The fab notes should mention something about the maximum depth of dimples in the pad due to the via-in-pad. So-called “flat pad” technology might be a good keyword in your notes.

Figure 3. Image Credit: Author - Micro-vias as a gateway to full HDI can be incorporated into EMI shields and QFP packages without compromising solderability.

So there you go, u-vias can help tighten up placement, shorten inductive loops, escape from “inescapable” pins and increase reliability of the overall assembly. The main cost is dealing with the materials that come with the technology. These benefits can be had on a board that only requires a single lamination cycle.

The other end of the price spectrum is a board composed completely of micro-vias. These boards will have numerous lamination cycles as all of the layers are build-up layers. Their construction will resemble that of the substrates that go between the chip and the board. They are common in phones, watches and assorted entertainment systems where they compete on both size and performance. The more extreme systems will add the complexity of flex circuits between different functional aspects of the design. When your board is using micro-vias to this extent, hats off to you! Meanwhile, getting started with the basics is pretty easy.