Via-in-Pad Myths and Realities
As component densities increase, so do placement and routing difficulties, and getting a complete PCB layout requires some creative routing decisions. At high densities, you might be tempted to place a via directly into SMD pads in order to make room on surface layers for other components. In fact, it is acceptable to place vias in SMD pads, but there are certain myths about when and how to place these vias.
To help designers make smart decisions about via-in-pad placement, this guide addresses three important myths surrounding this design practice. Things like BGA pitch and reliability are two of the main areas where via-in-pad usage comes into question; we’ll address these points in this article.
Via-in-Pad Increases Component Densities
The main reason to use via-in-pad is to increase component density in a PCB layout. This comes at the expense of higher cost. Appropriate use of via-in-pad requires plugging the vias and plating over to provide a solderable surface for SMD components. As long as this practice is enforced, via-in-pad can be used without assembly problems.
Myth 1: Via-in-Pad is Only For Fine-Pitch BGAs
It is true that via-in-pad is most often associated with high-density components like fine-pitch BGAs. The reason for this has to do with the space required for dog bone fanouts underneath a BGA. When the ball pitch in the BGA becomes too small, there will not be any room for vias in the dog bone fanout without violating clearances. The result is that the vias have to be moved into the pads in the BGA footprint in order to keep from violating clearances.
This BGA has enough room for a dog bone fanout.
Vias can be brought into the pads on a fine-pitch BGA, and in this case the vias can still be through-holes. One reason to do this would be to allow for additional routing space between pins on the BGA.
When the BGA pitch gets smaller (generally approaching 0.5 mm or smaller), you will be forced to use via-in-pad. When the pitch is small, the pad size may also be small, thus the via size could be below the typical 8 mil limit for mechanical drilling of through-hole vias. In this case, you now have to use blind/buried vias to reach the internal pads.
An example with a 0.4 mm pitch is shown below. In this example, the vias were required to be brought into pads on the PCB due to the fine pitch in the component, which creates small clearances between pins in the BGA. These vias are blind vias going to layer 2.
Blind via-in-pad with a 0.4 mm pitch component.
Although these two examples show how via-in-pad can be used in BGAs as pitches decrease, via-in-pad can technically be used in any component. When component densities are high, and there is not enough room to place a via with a connecting trace between two components, it is very convenient to put the via in an SMD pad. In this case, the vias need to be filled and capped in order to prevent solder from wicking to the back side of the board.
Myth 2: Via-in-Pad Makes SMD Pads Unreliable
The belief in this myth is that a via in the pad causes the pad to be hollowed out, and thus it could more easily detach from the PCB at high temperatures or after repeated cycling. In fact, the use of via-in-pad does just the opposite: it actually strengthens the SMD pad so that it can better adhere to the PCB laminate.
The reason for this is due to anchoring of the pad as provided by the via. The via will extend internally into the PCB and will have some anchoring into an internal trace or plane. This attachment to an internal conductor provides some mechanical strength that can resist thermal expansion and high temperature detachment from the surface of the PCB.
Myth 3: Via-in-Pad Reduces Via Inductance
This is not so much a myth as it is something requiring clarification. We have to clarify whether we are referring to the self-inductance of the via, or whether we are referring to the loop inductance for a current path that includes the via. These are not necessarily the same thing.
The total loop inductance for a current path that includes a via is the sum of all inductances along that path:
In short, using via-in-pad does reduce the trace portion of the loop inductance. This is because a trace is eliminated by placing a via directly into the SMD pad. However, simply taking a via and moving it into a pad does nothing for the via inductance unless the dimensions of the via are changed. Typically, the trace portion of the inductance (a few pF) is much smaller than the via inductance (~1 nF), so the reduction in loop inductance may be negligible.
Follow Via-in-Pad Best Practices
Because of the usage of via-in-pad for high-density PCB layouts, it’s possible that via-in-pad can provide much higher component placement densities. If you do plan to use via-in-pad, the vias must be plugged to prevent solder from wicking to the opposite side of the board and creating assembly defects. As long as this primary guideline is followed, via-in-pad can be used successfully to increase component density in a PCB layout.
Whenever you need to design and layout high density PCBs, use the complete set of CAD tools in OrCAD from Cadence to build your circuit board. Only Cadence offers a comprehensive set of circuit, IC, and PCB design tools for any application and any level of complexity.
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