Getting Started With Xilinx FPGA Board Design

FPGA boards are excellent platforms for prototyping specialty logic that will be later used in custom silicon, or for building unique systems that are reconfigurable. Because some processors do not implement the specialty logic or interfaces needed in some advanced designs, an FPGA is an excellent platform for building these systems and implementing custom logic. FPGAs offer many other advantages as we’ve discussed in other articles on this blog.

To help designers get started with more advanced FPGAs, we will show a single-board embedded computing platform that can be used as a host board for vision or sensing applications. The board will include several connectors for possible peripherals, including board-to-board connectors that can be used as the interface to a sensor board or cable interposer. This project is based around the XCAU part family from Xilinx, and we’ll show the PCB layout process for this type of component as part of the project.

Xilinx Artix FPGA Overview

The FPGA platform that we’ll use in this example project is the Artix UltraScale+ FPGA from Xilinx (Part number family: XCAU). This FPGA comes in multiple package options, offers high logic cell count, and provides IP support for many common high-speed interfaces and protocols. This FPGA platform is useful in diverse embedded systems applications, ranging from vision systems to embedded AI. The table below provides an overview of the capabilities of the XCAU part number family.

The board we will design here will include several components that enable on-board processing of large data streams, such as vision data or digital data from multiple sensors. There is enough processing power on this board to implement high compute applications such as embedded AI. Other components in the design include:

• A camera module connector that connects to the FPGA with a CSI interface
• Upgraded SFP transceiver for up to 16G optical data transmission (depends on matching IP and part number)
• DDR4 memory (8 GB capacity)
• A set of spare headers and indicator LEDs
• A pair of board-to-board connectors with LVDS connections

Schematics

The FPGA used to build the schematics is the XCAU10P-1FFVB676I, a fine-pitch BGA in a 676 ball package. The schematics were developed based on a reference design from Opal Kelly, a 3rd party vendor of development products for embedded systems. Their power supply strategy and interface selection were significantly modified to support a much higher number of high-speed differential I/Os, which also required more total current during full-scale operation compared to the reference design.

One thing you will notice in the schematics is a large number of differential pairs broken off to the board-to-board connectors. This is shown primarily on Banks 65 and 66.

High-speed differential I/Os on Bank 65 (left) and Bank 66 (right)

The differential pairs on Bank 66 are defined as 100 Ohm LVDS, but they could be redefined as another high-speed differential interface with equivalent impedance, or as groups of single-ended I/Os. These differential pairs are routed out to the Hirose board-to-board connectors shown on Page 1. The pairs on Bank 65 are defined as 85 Ohm CSI-2 and are routed to the camera connector on the top of the board.

Routing of differential lanes into Hirose connectors.

Input power is provided over a barrel jack connector and is protected with a reverse polarity circuit (MAX16914AUB+). Power management uses a simple strategy where a primary regulator is allowed to come online before all other regulators, but without the use of a power sequencing IC. This is done by taking advantage of a PGOOD output from the 0.85 V/16 A regulator. This regulator is required to turn on early before other regulators are allowed to start and bring the system online.

POWER GOOD from the 0.85 V regulator is used to enable other regulators in the design.

The VCCINT net provides the bulk of the power required by lower level I/Os on the FPGA, and it may need to support very high instantaneous currents during operation. Other regulators are needed to provide a range of voltages for the FPGA and peripherals, including 1.2 V, 1.8 V, 2.5 V, 3.3 V, and 5 V.

PCB Layout

The PCB layout was constructed in the typical manner with the FPGA located centrally in the PCB layout. The challenge with this FPGA is its fine pitch of 1.0 mm between SMD pads. This pitch is large enough that via-in-pad will not be needed to provide a fanout strategy through the internal layers. Based on the pinout and number of I/Os, the stackup included 8 layers with interleaved signal and ground.

The BGA fanout beneath the FPGA was achieved using 8 mil diameter/16 mil pad size through-hole vias with dog bone fanout. The vias could be oversized to 20 mil if greater reliability is needed. The pitch between the SMD pads is large enough that 15 mil wide traces could be used for PWR and GND connections through the vias. This ensured that the design could be built with conventional processes that would not incur excessive costs from HDI fabrication.

BGA fanout was achieved using 8 mil/16 mil vias.

To help keep layer count low, signals and ground were placed together on some internal layers (L3 and L6). Many of those signals were defined as controlled impedance signals, and as such they take advantage of reference planes on L2/L4 and L5/L7 to set their impedance to the target value (100 Ohms differential).  The impedance is also set by using GND on the internal signal layers (L3 and L6) in a coplanar stripline arrangement. Sufficient clearance required to set the impedance was 0.65 mm (approximately 25 mil).

Some groups of LVDS lanes coming off of the FPGA and being routed to the board-to-board connectors were length matched to each other. This is because certain differential interfaces, such as CSI-2 or JESD204C, might require length matching across a group of differential pairs. This allows these types of interfaces to be instantiated in certain banks (65 and 66) without requiring rerouting in the FPGA board. These lanes can still work as LVDS if desired.

Length matching is applied across some of the LVDS lanes to allow for timing-matched differential interfaces without rerouting.

The board does demand somewhat high current at the intended voltage levels due to the large number of switching I/Os. To ensure sufficient power plane decoupling against neighboring ground layers, large copper pour was used for power on L4 and L5. There are two good reasons for doing this:

1. This allows very easy power connections to be made across the FPGA and peripherals by directly connecting to the large pour layers.
2. The coplanar ground on neighboring layers still ensures we have low PDN impedance through most of the design.

To verify this design, it is recommended to simulate the board in a transient electromagnetic field solver, such as in Clarity. The goal would be to evaluate whether there are excessive edge emissions from the board due to the overlapping power planes. If a simulation were to reveal excessive emissions during switching, the simplest solution is to add two more GND layers (one between L3 and L4, and another between L5 and L6). This would provide additional decoupling to keep the PDN impedance low and it would ensure both sides of the stripline layers are always referenced to uniform planes.

The finalized layout from the top layer view is shown below. The regulators were placed on the top layer and some rails were routed as large pour sections to provide the required current with reduced switching noise.

Completed PCB layout.

Finishing the Design

As the design sits now, it just needs vendor IP, pin assignments in Vivado, and any required specialty logic or compatible application libraries. Once created, the design would be ready to boot and it can start capturing sensor and camera data. The design could then perform processing on-board or stream the data to an external system over its SFP connection.

This board could still be expanded in terms of its capabilities by breaking out more of the I/Os from the FPGA package. Currently, there are many open I/O pins on banks 65 and 66, and these pin groups could be used for differential interfaces or single-ended buses.

Some ideas for expanding the capabilities of the design include:

• Swap for a higher part number that provides
• Add an additional 1 Gbps Ethernet interface for lower-speed networking
• Replace the board-to-board connectors with equivalent pitch board-to-wire connectors
• Add an analog front-end for any analog sensors that might come into the board
• Add additional cameras (could reach a total of 4 or more)

If the design is expanded with these options, some of the regulators may need to be upgraded to higher part numbers (for example, in the TPS family) to ensure sufficient power is provided to any new peripherals. This might later demand a cooling strategy that should be considered by the system designer. If the FPGA part number is swapped, always make sure to verify the pinout when moving to a different part number; not all parts are pin-equivalent.

To access the project files for this design, click on the links below.

• XILINX XCAU PCB Design
• XILINX XCAU PCB Footprints

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