Signal Integrity Design Considerations for High Speed Design

August 1, 2019 Cadence PCB Solutions

3D high speed design and layout in Allegro

 

There is a saying in the PCB design community: there are those who already worry about high speed design, and those who will soon need to worry about high speed design. Ever since the introduction of TTL and faster logic families, designers have found that simple PCB layout arrangements were not adequate to maintain signal integrity. These high speed devices exhibit peculiar signal integrity problems when they are not laid out properly.

With devices that run at even modest data rates switching at speeds on the order of nanoseconds or less, every designer should take signal integrity design considerations seriously during high speed design. These high speed design techniques are geared towards ensuring that signals remain free of artefacts that can lead to high bit error rates, clock streams and serial or parallel data remain synchronized throughout a board, and transmission line effects are suppressed in long PCB traces.

With many high speed devices that incorporate wireless functionality or interface with external analog systems, grounding and layer stack design are also important. These aspects of high speed design affect EMC and grounding requirements, and designers should carefully design their layer stack. The right layer stack and grounding strategy will help a device pass EMC checks, suppress EMI, and ensure signal integrity in these mixed signal devices.

What Makes a PCB a High Speed Device?

When most engineers think of high speed design, they want to set a threshold in terms of the data rate in the device. In reality, the data transfer rate does not determine whether a given board operates at low or high speed. Instead, the signal rise time is the primary factor that determines whether a given device operates at low or high speed. This means that a board can operate at relatively low data rate (less than 1 Mbps), but it will still require high speed design techniques if the signal rise time is very fast.

The signal rise time affect three aspects of signal integrity: crosstalk, transmission line effects, and radiated EMI. These signal integrity problems are related to parasitic capacitance and inductance between neighboring signal traces, as well as a trace’s characteristic impedance. Devices designed for very high data rates require logic that transitions much faster between ON and OFF states. With faster rise times comes stronger crosstalk, stronger ringing, and greater likelihood that an interconnect will behave as a transmission line.

This is where a routing strategy, impedance-controlled design, and proper layer stackup become important for ensuring your traces can resist crosstalk and EMI, as well as suppress transmission line effects. Interconnect design strategies geared towards high speed design can ensure signal integrity and suppression of external radiated EMI in more complex systems.

High Speed Interconnect Design

Interconnects in your board carry your high speed signals around your board and should be designed to suppress or eliminate common signal integrity problems. Signal integrity design considerations, specifically with respect to interconnect design, involve impedance-controlled routing, proper stackup design, length matching tolerance, and termination network design for impedance matching during high speed layout.

 

Overshoot and undershoot as signal integrity design considerations

Overshoot and undershoot are potential signal integrity problems that can arise in high speed designs

 

Interconnect design is also related to layer stack design as your layer stack can provide shielding against EMI, determine the characteristic impedance of your traces, influence crosstalk between traces, and increase the chance your device will pass EMC tests. All these issues affect signal integrity throughout your board and whether you can implement impedance-controlled routing in your PCB.

Signal Integrity Design Considerations for High Speed Design

With all the signal integrity problems that can arise in a high speed board, there are some important design techniques to consider during the PCB layout phase. A poor layout can leave you searching for noise sources that don’t exist. Instead, consider the following points when building your next high speed PCB.

PCB Stackup for High Speed Design

Your layer stack performs a number of functions in high speed design and is a significant signal integrity design consideration. By far, the most popular design choice for ensuring signal integrity in multilayer boards with single ended traces is to route signal traces directly over a ground plane. Traces can be routed through the inner layers, but it is best to place inner signal layers between solid copper planes to prevent crosstalk and shield these traces from external EMI. Taking advantage of shielding provided by ground planes can also help you pass EMC checks.

If your board will include some analog functionality alongside high speed digital devices, you’ll need to carefully segment your digital and analog sections of your board so that analog signals do not interfere with digital devices, and vice versa. You’ll also need to carefully route analog within the analog section to prevent the same signal integrity problems that can affect digital signals.

Read more about designing your PCB stackup.

 

Layer stackup for a multilayer board

Example layer stackup for a high speed design

 

Transmission Line Effects in High Speed Design

The real factor that determines whether certain traces in your board should be designed as impedance-matched transmission lines is the length of an interconnect between a source and a load. When the time required for a signal to travel along a trace is longer than approximately one-quarter of the signal rise time, then the trace can behave as a transmission line. Impedance mismatches between the source and the trace, or between the load and the trace, will cause a signal reflection.

A signal reflection at the source will propagate a signal back into the IC package, but this is generally ignored in high speed design as signals reflected back into an IC are blocked thanks to the structure of transistors in the driver. Signal reflections at a load are much more important as they can cause ringing in an underdamped trace. Ringing refers to a transient oscillation in a trace, where the transient signal oscillates at its natural frequency. This is where a series termination resistor at the load is important for perfectly damping the trace and suppressing ringing.

If you’d like to learn more about transmission line effects, read about designing and simulating an impedance matching network.

Preventing Clock Skew and Signal Skew in High Speed Traces

Working with high speed clocks and signals requires precise length matching of traces throughout a group of signals within some allowable tolerance. When signals are sent to a load component, the signals will require some specific amount of time to switch between ON and OFF. Traces carrying data in parallel need to be precisely length matched to ensure that all signals reach the load at the same time. Similarly, traces with serial and parallel data streams must be length matched to the clock signal in order to ensure that the load IC switches at the right moment. Any timing skew that arises due to length mismatch will increase bit errors in the system.

If you’d like to learn more about this subject, read about compensating skew with trace length matching.

 

Screenshot of length-matched traces on a PCB layout

Length matching for high speed design

 

How Parasitic Capacitance and Inductance Affect Signal Integrity

Every conductive element in a PCB has some parasitic inductance, and multiple conductors together have some parasitic capacitance. Parasitics are inevitable, but their effect on crosstalk can be reduced with creative design techniques. The principle way to reduce crosstalk through parasitic coupling is to route traces very close to their reference plane, or to route traces as differential pairs.

Parasitic capacitance and inductance can become a major problem in devices with very fast rise time (i.e., 10 Gbps or higher), even on traces that are designed as impedance-matched transmission lines. Variations or asymmetries in trace geometry will create impedance discontinuities throughout a trace due to parasitics, which can lead to reflections at various points along a trace. Overcoming this problem relates back to the routing strategy mentioned above. Traces should be precisely length matched and routed such that parasitics are consistent throughout the length of the trace, which requires consistent trace spacing and loop area throughout an interconnect.

Here is some more information on parasitic capacitance and inductance.

Impedance Matching Network for Termination

There are a variety of termination networks that can be used to match the overall impedance of a trace to the load. This will eliminate signal reflection at the load. The best strategy is to use both strategies. Placing an appropriate series termination resistor at the load will suppress ringing by perfectly damping the trace, but this can change the value of the impedance mismatch. Placing a termination network will then ensure that the combined trace and series resistor will match the impedance at the load.

If you’d like to learn more about transmission line effects, read about designing and simulating an impedance matching network.

Bringing Your Analysis and PCB Design Tools Together 

Preventing signal integrity problems in high speed design is all about having the right layout, routing, and stackup management features in your PCB design software. When coupled with signal integrity and circuit analysis tools, you’ll have everything you need to address signal integrity design considerations in high speed design.

 

High speed layout in Allegro

Just one of many high speed designs you can create with Allegro

 

Cadence’s full suite of PCB design and analysis tools are adaptable to any application, including high speed design. The SI/PI Analysis Point Tools provide designers with signal integrity and power integrity analysis features that are geared towards PCBs and IC packages. You’ll have access to a complete electronics design and analysis solution when you work with the industry-standard features from Cadence.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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