How To Ensure Star Topology Signal Integrity In PCB Design

May 23, 2019 Cadence PCB Solutions

Star topology signal integrity will require more than a telescope

 

Astrology has been a hobby of mine for years. Recently, my community of stargazers was abuzz over the appearance of the Scorpio constellation in the sky. I tried to catch the zodiac symbol itself, but it’s more than a little difficult to see the full configuration, especially with any degree of light pollution in the area. I saw nothing but blurs and tiny specks of light in the darkness.

While the star topology in your PCB design certainly shouldn’t be affecting your fortune, romance, or side projects, it will contain risks to signal integrity. You may find the communication between integrated chips (IC) reduced to a jumble of electrical fluctuation with improperly managed star topology signal integrity. Find out what to watch out for and how to manage it successfully below.  

What Is Star Topology?

With a star topology, a series of devices, including transmitters and receivers, are connected via a single node. In PCBs, this is commonly seen through ICs that are connected on a single bus. Common signal integrity measures will always apply to these designs; however, this single bus technique usually involves clocking and data signal.

For example, the serial peripheral interface (SPI) signal is often routed with a star topology, with the originating signal from the driver traveling on the bus before splitting to the respective receiving ICs on the PCB. At a glance, it may look nothing like a star as it is so often denoted in schematic representation, but it has all the concerns of star topology routing.

Design Considerations Over Star Topology Signal Integrity

As with all things based on signal and frequency, signal speed is going to affect the star topology signal integrity. If you’re dealing with signals in the realm of kHz, you won’t really need to worry about signal integrity issues on a star topology. However, if your design involves hundreds of MHz or GHz, you’ll want to pay special attention to how the traces are routed and other aspects in a star topology design. As always, trying to match rise time with frequency in respective domains will make signal integrity more manageable.

There are two primary issues that may wreak havoc to the transmitted signal on a star topology layout. The first is clock skew. Clock skew denotes a phenomenon when the receivers on the same bus are receiving the clock signal at different times. Clock skew can be a major problem when the clock signal is of a significant delay as compared to the data pulse. This can result in certain data being launched twice or never at all.

 

High speed signals traveling from a train tunnel

High speed signals open up star topology to signal integrity issues.

 

The second phenomenon that you need to be concerned about is signal reflections. Signal reflection happens when there is an impedance mismatch between the transmitter and the load. Load indicates the trace impedance and the impedance of the receiver IC. Reflection becomes a real concern at high frequency when the rise time of the signal becomes lesser than the trace length.

To understand signal reflection, picture waves crashing onto the seashore. When a wave hits the shoreline, there’s a reflecting wave that travels backward and crashes into the next incoming wave. When that happens with data signals, they become distorted and affect the signal integrity. Signal reflection is not exclusive to star topology but when you have multiple data signals converging on a single node or bus, the problem becomes intensified.

Ensuring Signal Integrity for Star Topology in PCB Design

The next time you’re working on a PCB design that involves star topology and is of high speed, you’ll want to prevent both clock skew and reflections.

Clock skew occurs in a PCB because the traces of the clock signal from the transmitter to the various receivers differ. The difference, which may not be obvious to the naked eye, can mean one IC getting the clock signal later than others. So, you’ll need to ensure the clock signals between the source and all receivers are of the same length. You could also add a matched length constraint during your design to all such signals whose length needs to be matched within certain tolerances.

 

Component placement and choices can help work through signal integrity issues

Adding a terminating resistor can eliminate signal reflection

 

The solution to avoiding problems with signal reflection is simple. You’ll need to check out the impedance of the driver IC and match it with a terminating resistor of the same value. Then, you’ll place the terminating resistor in series to the driver. This will provide a definite matching impedance and prevent the signal from bouncing back from all the receiving nodes on the star topology.

Unfortunately, not all signal integrity demands are simple. To be safe, you’ll want to verify that you don’t have any issues with signal integrity with PCB tools offered by Cadence. Specifically, the SI/PI analysis tool will give a clearer picture on how the signals look like on anything in a star topology network.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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