How Technology Creep Has Impacted PCB Design

Let’s start with a bit of living history. I still remember using punch cards for our elementary school records. Back in the day, we pulled the vacuum tubes out of our TV set to test them and get replacements, if necessary, at the grocery store. Can you imagine having user serviceable parts on your flat-panel TV where taking the back off of the unit was part of the routine ownership experience? It was nuts.

Those unreliable televisions with low-resolution black & white images have had to adapt to the times. Solid state components replaced the tubes and then integrated circuits replaced the discrete components. The hand wiring of the first generation televisions became two-sided boards with etched circuit patterns.

PCB Design in those days was a craft starting with colored pencils and finally using clear mylar and adhesive backed black paper (tape) to generate the circuit pattern. Applying the tape to the mylar over the penciled in lines was called “taping out” and that is still the term used for generating the document package with the CAD tools.

Figure 1. Image Credit: Author - The Stone Age of electronics: What if you split a boulder and found yourself in a matrix of stone?

The first generation of integrated circuits were the same as the discrete components in that they had pins that were inserted through the PCB during assembly. The leads were subsequently soldered from below by dragging the board across a molten bath of tin/lead.

Continuous Shrinkage of Electronic Components Drive PCB Technology

Standardization among the chip vendors meant that most devices were 0.3 inches wide with pins spaced at 0.1 inches or 2.54 mm. This tenth of an inch pitch for through-hole pins is still a valid way to go for a lot of applications. The first wave of surface mount components moved the pin pitch down to 0.05” or 1.27 mm and that is the last node before 1 mm. All downward increments since then have been on a metric footing.

Each increment in SMD pin pitch from 0.80 to 0.65 to 0.50 to 0.40 and 0.35mm has required a revolution in how boards are fabricated. Geometries and tolerances get finer and finer as we go which is making new hurdles for the PCB Designer. Finding substitute components that fit in the same footprint as the original part is next to impossible.

Ancient Technology is Still in Use

Audiophiles as well as the makers of the musical content are suckers for old fashioned circuitry. Music for the masses went digital some time back so it’s no surprise to run into a CODEC device that is only available on a 0.4 mm pitch Ball Grid Array (BGA) package with about 90 pins.

If we step back and compare the 100 mil pitch Dual-Inline-Package (DIP) to the 16 mil pitch full rectangular BGA package, it’s clear that the designer has had to evolve along with the technology. Pins on through-hole components have access to every routing layer by default while the surface mount parts can be designed around micro-vias. Once the pitch of the BGA device gets below 0.65 mm, micro-vias become the only viable solution.

High Reliability Design Limitations

Aside from hifi consumers and musicians, there are lots of industries where the reliability requirements are such that they cannot use micro-vias on their boards. It can be a struggle to find components that work in an IPC Class III world.

A typical Class II capture pad for a microvia is 250 microns in diameter. Drawing on field experience, we had to go up to 320 microns on a microvia pad for projects including Lidar sensors, comm satellites and augmented reality headsets. We relied on quad flat pack (QFP) packages and BGAs with wider pin to pin dimensions.

Meanwhile, the chip companies, particularly those in the mobile processor business are focussed on making the chip as small as it can be. Low power usage is a happy byproduct of going with these fine-pitch devices. That makes these leading edge devices a valuable proposition for fixed locations - server farms. Power is one of the main costs of running a data center.

Looking back around 20 years, my first edge router had four separate processors and a separate memory controller, each about 450 pins. It was a difficult layout to match all of those lines from the CPUs to the memory controller. In hindsight, it was child’s play next to the 1300 pins and multiple cores on today’s system on a chip (SOC) solutions.

It may have taken us a lot of iterations to shrink down from there but we’re not done. The skill set from five years ago isn’t enough for today and today’s skills will be obsolete soon enough. That is the price to pay as we work in technology. Nothing is static. A lot of numbers are used in this story to show that we grow while shrinking.

The ultimate example has to be cell phones. The first ones didn’t have a camera or GPS, WiFi, NFC, Bluetooth or even any apps to download. It didn’t exactly fit in your pocket either. The players in this space have gone head to head on specifications adding more screen resolution and longer battery life to each successive iteration.

Note that battery life is added by adding cells which takes away from the space left for the printed circuit board. So, even though one phone will have a larger screen size, the PCB area is unlikely to benefit from the bigger form factor.

Figure 2. Image Credit: Bettmann/Getty Images - A Motorola exec demonstrating an early cell phone circa 1973.

The squeeze on PCB space in the name of added features also applies to tablets and laptops. The race for resolution and battery life have also played out along with never-ending wireless upgrades. Going back to 2014, my first laptop motherboard was huge. It went almost all the way across the chassis with a little flex for a USB-C port on the other side. That was roughly 10 inches by 6 with two huge cut-outs for cooling fans. The last laptop motherboard I did for Samsung’s Chromebook Pro could fit in your hand.

Figure 3. Image Credit: Author - High density meets low layer count for consumer electronics like this Chromebook main logic board.

Shrinking line widths drive thinner layers of copper due to etch process limitations. Micro-vias drive thinner dielectric materials because it is difficult to plate holes that are deeper than they are wide. We’ve had to switch from mils to microns to match the precision as we scaled down the geometry. Balancing these limitations with the impedance requirements of signals and power delivery requirements of hyper-integrated circuits pushes us to new levels of complexity.

What is happening out there on the leading edge is quite a bit of simulation and characterizing small segments of the overall circuit before moving on to coexistence of the integrated whole. The interdependencies, especially in the wireless links can give rise to unforeseen peaks or spurs in the waveform. The regulatory bodies are not going to put up with that! We usually get at least one prototype to uncover the unknown unknowns.

To paraphrase Gordon Moore, our workload doubles every eighteen months. The longer you hang around the more you have to adapt. Silicon leads the way. Sometimes, there are conflicts between what the chip vendor wants you to do and what the fabricator is capable of doing. Unrealistic hole tolerances are one of the most common discrepancies. Getting to the point where we can turn a concept PCB into a working PCBA is where our value lies. The only constant is that we’re dealing with a moving target.