Fault Tree Analysis Structure for Electronics Manufacturing

September 23, 2020 Cadence PCB Solutions


Globe with FMEA and production topics

After graduating highschool, during one particularly boring night in my small town, my friend and I decided to climb the town’s water tower. The risks of getting caught or hurt never crossed our juvenile minds. Despite all the risks, neither of us did any type of risk analysis—we didn’t heavily deliberate on using FTA vs. FMEA analysis, or even consider doing a simple pros/cons list.

After working in the electronics industry for many years, I finally understand, appreciate, and  utilize risk analysis. Without some type of risk analysis, we blindly trust that designers, vendors, and manufacturers use quality components and rely on quality processes that lead to failure-proof products. Although this level of trust may speed the distribution of products to customers, it may also lead to catastrophic failures. Methodical risk analysis techniques are necessary to help engineers remove guesswork, identify risk, and assess consequences.

The Importance of Risk Analysis

When engineers identify risks, we think in terms of events, sources, and threats. Although we could define an event within the context of end-of-year holiday parties, events have a much more negative connotation for projects: an event prevents projects from achieving objectives. Every event culminates in a negative result—called a threat—and has elements called sources that work as triggers. Any attempt at identifying risk must consider the chain of defining project objectives, sources of risk, possible events, and threats to those objectives.

For example, a project might have objectives that focus on producing next-generation avionics for passenger aircrafts. From a PCB design perspective, the source of risk might include the availability of high-tolerance components and the possibility that an interrupted supply chain forces a design team to select lower-tolerance components for production. The threat becomes evident during testing, when the product fails during simulations that show the component failure during in-flight conditions.

When we assess risks, we organize all the risks that we have identified according to the severity of the threat and the probability of an event occurring. To simplify this a bit, we can construct a matrix based on the product of severity and probability. We call this product the composite risk index (CRI). A high value for the CRI translates into a higher priority risk. With the CRI values in hand, we can prioritize risks and determine whether we want to mitigate or accept the risk.

 Composite Risk Index.

Fault Tree Analysis

Fault Tree Analysis (FTA)  uses a top-down approach to discover the cause of a failure. Each graphical fault tree consists of two different types of events and logic gates that connect events. Boolean logic describes the logical relationship between low-level, undesired system states—or basic events—that can cause the failure of a system, or top event. An engineering team can use one or more fault trees to show combinations of failure states of a component. We can use the symbols shown in the following table to build a map that shows how the events unfold.

 Table depicting symbols to show how events unfold.

Because FTA works from the top-down, we begin the process by defining a primary failure. The primary failure becomes the top event in a fault tree. From there, we use available technical information to identify basic events and logic gates to show the relationship between the primary event and the basic events. Then, we follow the same process to identify other basic events and show the logical relationships to the primary event. Each logic gate represents a fault state. While the next figure shows a small sample of an FTA, actual fault trees have many branches and events.

  Sample of an FTA.

The analysis portion of FTA begins with cut sets—or a set of combined basic events that can cause the primary event. As the analysis continues, the cut sets reduce to minimal cut sets or the smallest number of events that can cause the primary event. Every analysis can conclude with a probability calculation for the minimal cut set. After a team assigns probabilities to each basic event, they can use reliability and probability equations to determine the reliability of the system or the probability of the top event occurring. 

Failure Mode and Effects Analysis

As the name implies, Failure Mode and Effects Analysis (FMEA)  determines possible failure modes and considers the level of impact of those failure modes on the performance of a system. In contrast to the FTA approach that only studies critical or safety systems, FMEA considers all potential failure modes and then identifies, evaluates, and prioritizes the possible failures. FMEA works well during the design stages of a circuit or product, and provides value by showing possible operational challenges or by eliminating cascading problems.

Within the FMEA approach, every failure mode receives a risk score based on severity (S), occurrence (O), and detectability (D), and receives a Risk Priority Number that equals the product of the three factors. In most instances, design teams will continue analyzing failure modes that have an RPN above 100 and take corrective actions.  The FMEA approach also allows teams to assess the impact of a failure on the entire system operation.


The notion of FTA versus FMEA conjures up the image of two Ninja-clad opponents carefully circling one another,  looking for an opening. Instead, the opposite is true. In most circumstances, engineering teams combine both techniques to gain a thorough appraisal of risks. Using this hybrid approach allows teams to take advantage of the strengths of FTA and FMEA while minimizing their limitations. 

Using a hybrid FTA/FMEA, or FMEA/FTA, approach allows teams to analyze increasingly complex systems that include large numbers of critical components that impact functionality and safety. The benefit of the hybrid approach occurs through an extensive analysis of conditions that can lead to an undesired event and the reasons that faults exist.

A comparison of FMEA vs. FTA analysis is less important, since both techniques offer numerous benefits. It is suggested that combining the two techniques together to identify risks accurately and effectively is the best approach to take. To learn more about FMEA or FTA analysis, or to search for a component for your latest project, visit the Cadence PCB Design and Analysis overview page. The cutting edge PCB design solutions from Cadence will make any electronics project easy. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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