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Redistribution Layer Process Flow for 3D ICs

Published Date
Author Cadence PCB Solutions

Key Takeaways

  • Implementation of a redistribution layer enables significant space savings and standardized I/O footprints in advanced ICs.

  • RDL fabrication using polymers involves spinning, photolithography, etching, sputtering, and electroplating processes.

  • Cu damascene process offers finer line widths, smaller pitches, and reduced dielectric layer thickness in RDL structures.

Wafer before cutout of dies containing a redistribution layer

Depending on the chip’s process nodes, foundry capabilities, and chip’s design requirements, the redistribution layer process flow may vary

As integrated circuit (IC) density increases and IC pad-pitch and size shrink, the conventional package substrates become inadequate to meet the requirements of advanced ICs. The use of a redistribution layer (RDL) process flow,  enables the utilization of a larger chip area, resulting in significant space savings, standardized I/O footprints, and more cost-effective substrates for 2.5 and 3D ICs.

However, creating a redistribution layer process flow is a complex and nuanced procedure that varies depending on the chip fabricator, chip requirements, and desired structure. Read on as we explore two advanced methods for redistribution layer fabrication: RDL fabrication using polymers and fabrication through the Cu Damascene process.

Redistribution Process Flow Variations

Fabrication by Polymers Process

Cu Damascene Process

Involved Sub- Processes

Spinning, photoresist and mask, photolithography, etching sputtering, and electroplating

Plasma-enhanced chemical vapor deposition, photoresist, and mask, photolithography, reactive ion etching, sputtering, chemically mechanical polish, sputtering, electroplating

Passivation layer thickness

6 to 7 um

1 um

Redistribution layer thickness

3-4 um

2.6 um

Resulting RDL Structure

RDLs and passivation are usually thicker

Finer line widths, smaller pitches, reduced dielectric layer thickness

Redistribution Layer Process Flow Fabrication Using Polymers 

The first redistribution layer process flow method involves the use of polymers such as polyimide (PI), benzocyclobutene (BCB), polybenzo-bisoxazole (PBO), and fluorinated aromatic AL-X 2010. The fabrication process using polymers is through the following steps:

Creating the First Redistribution Layer 

  1. Spin the selected polymer, such as PI or BCB, onto the wafer and cure it for 1 hour, forming a 4-7 um-thick layer.

  2. Apply a photoresist and mask, and utilize photolithography techniques to open vias on the selected polymer layer.

  3. Etch the polymer to create the desired vias.

  4. Remove the photoresist.

  5. Sputter titanium (Ti) and copper (Cu) onto the entire wafer.

  6. Apply photoresist and mask, then use photolithography techniques to open the locations for redistribution traces.

  7. Electroplate Cu into the photoresist openings.

  8. Strip off the photoresist.

  9. Etch off the Ti/Cu layers. This completes the first redistribution layer (RDL).

To create any desired additional layers, repeat the steps above. 

Creating Under-Bump Metallurgy (UBM)

  1. Use your desired polymer and spin it onto the wafer, allowing time to cure as with step 1.

  2. Apply a photoresist and mask, then use photolithography techniques to open vias on the polymer for bump pads and to cover redistribution traces.

  3. Etch the desired vias and remove the photoresist.

  4. Sputter Ti and Cu onto the entire wafer.

  5. Apply a photoresist and mask, and use photolithography techniques to open vias on the bump pads, exposing the areas with UBM.

  6. Electroplate the Cu core, strip off the photoresist, and etch off the Ti/Cu layers.

  7. Finally, apply electroless nickel and immersion gold to complete the UBM 

The resulting RDL structure will have polymers as passivation and Cu plating as metal layers. The passivation layers will have a thickness of about 6-7 um, while the RDLs measure approximately 4 um in thickness.

Redistribution Layer Process Flow by Cu Damascene

Another approach to the redistribution layer process flow involves the Cu damascene process. The fabrication steps using the Cu damascene method are outlined as follows.

First Redistribution Layer Creation with Cu Damascene

  1. Deposit a SiO2 layer through plasma-enhanced chemical vapor deposition (PECVD).

  2. Apply a photoresist and mask, then use photolithography techniques to open vias on the SiO2 layer.

  3. Perform reactive ion etching (RIE) of the SiO2 to create the desired vias.

  4. Strip off the photoresist and sputter Ti and Cu onto the entire wafer, followed by electroplating Cu.

  5. Chemically mechanical polish (CMP) the Cu and Ti/Cu layers, completing the via connecting the TSV to the first distribution layer.

  6. Repeat step 1, depositing another SiO2 layer with PECVD.

  7. Apply a photoresist and mask, then use photolithography techniques to open the locations for redistribution traces.

  8. Repeat steps 3-5: RIE to create vias, stripping the photoresist, sputtering, electroplating, and CMP. 

  9. Finally, CMP the Cu and Ti/Cu layers, thus completing the first redistribution layer.

Process Flow for Additional Redistribution Layers and UBM

  1. First, form the via connecting the first and second redistribution layers by repeating steps 1-5.

  2. Then, to create a second redistribution layer, repeat steps 6 through 9. Through this process of adding interconnecting vias and redistribution layers, additional layers can be created. 

  3. To create the UBM, use PECVD to deposit an SiO2 layer, as with step 1.

  4. Apply photoresist and mask, then use photolithography techniques to open vias on the SiO2 for the desired bump pads and to cover the redistribution traces.

  5. Etch the desired vias on the SiO2 and strip off the photoresist.

  6. Sputter Ti and Cu onto the entire wafer.

  7. Apply photoresist and mask, then use photolithography techniques to open the vias on the bump pads, exposing the areas with UBM.

  8. Electroplate the Cu core and strip off the photoresist.

  9. Etch off the Ti/Cu layers.

  10. Apply electroless nickel and immersion gold to complete the UBM.

This Cu damascene method enables the creation of RDLs with finer line widths, smaller pitches, and reduced dielectric layer thickness compared to the polymer-based approach. In general, RDLs fabricated through this Cu damascene technique have a minimum RDL line width of 3 um. The thickness of the first and second redistribution layers is 2.6 um, with a passivation thickness of 1 um between RDLs.

As we’ve discussed, the redistribution layer process flow 3D IC integration can be achieved through different methods. While the polymer-based method involves the application of polymers like PI or BCB and the electroplating of metal layers, the Cu damascene process uses SiO2 layers and copper deposition. Each method has its advantages and contributes to the realization of RDL structures 

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