DDR4 Routing Guidelines for PCB and the Advancements in PCB Architecture

One of the things I enjoy most about the field of technology is the constant advancement. I know for some, there is a preference for a more static environment, but for me, I prefer a more dynamic atmosphere. With that in mind, there isn’t a more dynamic landscape than that of the world of computers.

There are always advancements and newer iterations waiting to be experienced and explored. If you are like me, building a new PC from scratch is a gratifying experience, especially when there is a new generation standard to experience.

This brings us to the topic of RAM or Random-Access Memory.  To be more specific, DDR4 RAM, which happens to be the current generation standard in the market to date. The importance of RAM is universally known, and if you ask any computer or network engineer, they will agree that you can never have too much RAM.

The Advancements in PCB Architecture with the Implementation of DDR4

As previously stated, the landscape in the field of computer technology is in constant flux. With the onset of new standards comes the need for a change in device architecture. That statement is equally true when addressing the generational standards change from DDR3 to DDR4.

These advancements in random access memories also bring about a significant increase in overall performance. Therefore, to be able to utilize the newest RAM requires changes in PCB design. Just as it did when the standard for USB advanced from USB 2.0 to USB 3.0. These types of changes are continuous and necessary as the demand for more processing power, better performance, and higher levels of functionality, continue to drive the advancement of the industry.

Although most people will not notice or see the needed architectural changes required by PCB designs, it does not diminish the importance of these critical changes.

What is the PCB Layout Changes Needed for DDR4 Implementation?

DDR4 or Double Data Rate 4 comes in two distinct module types. So-DIMM or small outline dual in-line memory modules (260-pins) that are in use in portable computing devices like laptops. The other module type is DIMM or dual in-line memory modules (288-pins) that are in use in devices like desktops and servers.

So, the first change in architecture is, of course, due to the pin count. The previous iteration (DDR3) uses 240-pins for a DIMM and 204-pins for a So-DIMM. Whereas the previously mentioned, DDR4 uses 288-pins for its DIMM application. With the increase in pins or contacts, DDR4 offers higher DIMM capacities, enhanced data integrity, faster download speed, and an increase in power efficiency.

Varying types of DDR RAM chips.

Accompanying this overall improvement in performance is also a curved design (bottom) that enables better, more secure attachment, and it improves stability and strength during installation. Also, there are bench tests that confirm that DDR4 offers a 50% increase in performance and can achieve up to 3,200 MTs (Mega Transfers per Second). 

Furthermore, it achieves these increases in performance in spite of using less power; 1.2 volts (per DIMM) instead of the 1.5 to 1.35-volt requirement of its predecessor. All of these changes mean that the PCB designers must reassess their design approach for the implementation of DDR4.

DDR4 Design Guidelines for PCB

It is understandable that if you want your electronic device or component to perform at an optimum level, it requires precise and accurate PCB design, and this includes the implementation of DDR4. In addition to the need for design accuracy, one must also adhere to today’s memory requirement demands.

PCB designers must also take into effect various other factors as well. Such as space allocation and critical connections. There is also a need to govern the initial design stages because designs must satisfy routing topologies and the design specifications for a successful implementation.

PCBs should follow routing and best practices (PCB) to manage data effectively. If there are any deviations from this practice, it can result in several issues, including susceptibility and radiated emissions. PCB Designers should also utilize the appropriate techniques for large-scale fan-outs, high-edge rates to maintain low bit-error rates, and data ranges between 1.6 and 3.2 Gbps. Again, without proper design techniques, your PCB will experience signal integrity issues and lead to crosstalk and the resulting (excessive) jitter.

DDR4 Routing Guidelines and Length and Spacing Rules

In PCB design, to achieve the optimum routing path, it requires both proper DIMM connector placement and proper memory chip use. In general, DDR4 SDRAM requires shorter routes and the appropriate spacing for peak timing and optimal signal integrity. PCB designers should also employ pin swapping in the relevant signal groups. In addition, during implementation, one should avoid routing signals over voids, routing signal layers next to each other, and reference plane splits.

In conjunction, you should also route memory interface signals between power layers or the appropriate ground (GND) whenever feasible. Additionally, you can help reduce or eliminate transmission velocity differences by routing the DQ (Input/output data), DQS (Data strobe), and DM (Data mask) signals in the same byte-lane group on the same layer. Also, due to the lengthier propagation delay of the clock signal compared with the DQS signal, the clock signal trace usually requires a length longer than the most extended DQS trace in dual in-line memory modules.

Finally, you must keep in mind that every board stack-up is different, and so areis the spacing requirements. Thereby it is necessary to utilize a field solver (Clarity 3D Solver) to establish crosstalk lower than -50dB between critical signals. Note: Clock to DQS has no length requirement, but the clock to command/control/address does have a length requirement. However, the length requirement is dependent on Dk (permittivity) of the material and the loading at each SDRAM.

DDR4 Layer Assignments and Data Lane References

It is acceptable to allocate the DQS, DQ, and DM nets to any available internal strip line layer in a stack-up. Whereas the Address/Command/Control and Clock should be routed on layers closer to the SDRAM to minimize via coupling.

The Address/Command/Control SDRAM vias should have added vias connected to ground (shadow vias) at each SDRAM to reduce via coupling.

Also, Address and Control reference power or ground depending on the controller. It should be noted, that DIMMs have address and control reference power, whereas onboard BGA’s (ball grid array) rarely have the address and control reference power.

DDR4 can add an immense amount of complexity to your designs, but smart guideline adherence can relieve this.

DDR4, like its predecessor (DDR3), requires a new design approach when considering implementation. There are obviously several changes in design requirements to accommodate the upgraded performance, but it is a side effect of innovation. However, following the proper design and topology techniques will yield the highest degree of performance from this new, now current generational standard.

Whether you’re implementing any form of DDR memory, or just working through a particularly signal-demanding design, Cadence’s suite of design and analysis tools. Allegro PCB Designer gives you not only the layout solution you need to place and route components properly, but a whole array of tools to augment analysis and production that will be sure to have your design polished quicker than you can say ‘double-data rate.’ 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.