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CMOS Power Amplifier Design Tutorial

Key Takeaways

  • The differences between series and parallel amplifier networks.

  • A list of commonplace topologies and when circuit needs dictate their usage.

  • A direct comparison of series and parallel amplifier network characteristics reveals relative strengths and weaknesses.

TO-92 packages on tape

The core of this CMOS power amplifier design tutorial: transistor networks come down to series and parallel configurations.

Modern electronics rely on amplifier networks to boost voltage, current, or power signals to appreciable levels for further use. Instead of using high voltage or current signals directly from a source that could impact device parameters (primarily when conductor features become very small), amplifiers allow for creating new signal levels as necessary. While many amplifiers exist, power amplifiers are physically the most demanding as they usually represent the final amplification stage before output. Amplifiers can build from discrete components, but smaller form factors may require an integrated approach. This CMOS power amplifier design tutorial will give product developers an idea of the different topologies and considerations for optimal outcomes.

Power Amplifier Class Comparison




A - single device that operates on full conduction

Simple circuit, small layout No warm-up time No crossover distortion

Extremely power inefficient due to continuous conduction Limited applicability Poor service life

B - two devices switch conduction every 180° of the signal cycle

Massively improves power efficiency over A class

An inability to switch between devices instantaneously causes crossover distortion

AB -a compromise between A and B classes that reduces power efficiency by increasing the conduction period of each device

Greatly reduces crossover distortion by shrinking conduction dead zone Can be further improved with a negative feedback loop

Worse power efficiency than class B, already a somewhat inefficient class

C - a single device that conducts less than 50% of the signal cycle’s period

When tuned, it resonates at the carrier frequency for adequate power efficiency without distortion

Operates only at a single frequency, power efficiency rapidly falls away from this value

D - adds pulse width modulation (PWM) for a more optimal conduction cycle

Extremely high efficiency Since transistors operate as switches, there is no need for a digital-to-analog converter (DAC)

Relatively few, if any

A Fork in the CMOS Power Amplifier Design Tutorial: Series vs. Parallel

CMOS power amplifier integration has many apparent benefits to miniaturization and cost, but there exist difficulties moving from a discrete component design. CMOS amplification intimately links with RF for wireless applications and the nature of high-speed design results in a significant loss operating at an acceptable power output. Initially, a high-speed design resulted in efficiency levels that today would be untenable. Low-loss impedance transformation networks using off-chip components arose to alleviate inefficiencies, but this solution lacks scalability, forming a performance and cost bottleneck.

Central to CMOS amplifier design is achieving sufficiently high output power with small voltages. Doing so requires the combination of individual CMOS transistors to form a power amplification network. Two primary approaches are available:

  • Series networks stack multiple transistors and operate them above recommended voltage levels (short of breakdown voltage).
  • Parallel networks merge the output of several transistors to meet power goals.

There are numerous distinct arrangements for both styles of amplifier design.


  • Cascode - This configuration utilizes a pair of amplifiers: one common source and one common gate. Signal inputs drive the common-source amplifier, whereas the common-gate amplifier is AC grounded. The cascode greatly increases output resistance and reduces capacitive feedback while exploiting the transistor breakdown voltage characteristics. Since recommended voltage levels are primarily established by the drain-to-source junction, operating the transistor network between the common gate and common-source shares higher voltage levels without reducing the performance or service life of the transistors. There are drawbacks, notably that more strain is placed on the common-gate transistor than the common-source transistor, with the former functioning as a sub-optimal switch, reducing power efficiency. Still, careful network design greatly elevates power efficiency despite these losses.
  • Totem pole - A totem pole or beanstalk amplifier reduces the voltage swing experienced by the gates of the transistor network with voltage division. Partitioning the gate voltage this way ensures that the drain-to-source voltage similarly divides to avoid reaching breakdown voltage at the junction. This topology encounters issues at high-speed frequencies as the propagation of the signal up the gates’ bias ladder can lead to phase shifts that reduce power at the output and potentially introduce distortions on the line.
    • Stacked transistors - This variant of the totem pole relies on transformer input coupling to provide the input signals. A capacitor connects the source and gate of each transistor in the network that shorts at high frequencies to allow the gate-to-source voltage to exceed the drain-to-source voltage threshold.


  • Doherty - A Doherty network, at its core, improves the average efficiency of the amplification with an auxiliary amplifier that only contributes during periods of elevated load-pull. A low-power region requires only the main amplifier that can operate anywhere up to the maximum output. If power demands increase at peak output, the auxiliary amplifier kicks in to cover the difference up to full output between the two amplifiers. A quarter-wave transmission line after the main amplifier inverts the impedance such that the impedance seen by the main amplifier decreases as the auxiliary amplifier ramps up; this strategy more effectively combines the generated power. A lumped element model can be used instead of transmission lines for on-die space savings, with a π (pi) filter generally preferred over a T filter due to the lack of inductors.
  • Wilkinson Power Combiner - Like Doherty amplification, a Wilkinson power combiner uses quarter-wave transmission lines to combine multiple inputs in-phase for increased output power. The Wilkinson Power Combiner can fabricate directly onto the board substrate with copper traces or from a lumped element model; cable solutions can also serve a similar role. The high isolation between the input lines prevents crosstalk. A similar solution is achievable with heterojunction bipolar transistors. 

Further Investigating Series and Parallel Characteristics

Comparisons are necessary when evaluating two methodologies. Like most questions in engineering, there is neither a right nor wrong answer but rather a decision of applicability to the circuit requirements. A series power amplifier design greatly endears itself to large power outputs within a small package. However, designs must adjust for efficiency losses from the push-pull interaction that depresses performance.

There are a few alterations that can achieve the desired effect. One is adding a small gate capacitance to each transistor that acts as a capacitive voltage divider. Placing capacitance on the gates creates the correct voltage swing at the drain and the gate to remain in phase while reducing the overall voltage swing at the gate and source for transistors in the common-gate and common-source combination. This pattern can iterate over a series configuration such that every gate of each transistor has matching voltage swings. At the same time, the total output increases up the ladder from ground to source.

In general, for a parallel amplifier network and a series amplifier network containing n number of transistors with the same source and output power,

  • The series network has n-times higher voltage gain, power gain, and input impedance, with an output impedance n2 higher.
  • The parallel network has n-times higher peak drain current.

Cadence Solutions Amplify Design Resources

This CMOS power amplifier design tutorial is a taste of a growing field due to ongoing miniaturization and power efficiency demands. Central to any power design will always be rigorous simulation and prototyping to ensure theoretical performance matches experimental without significant deviation. Cadence’s PCB Design and Analysis Software suite incorporates sophisticated models to reduce time and revisions during the prototyping stage. For layout, OrCAD PCB Designer gives development teams an easy-to-use ECAD environment that seamlessly integrates with other Cadence tools to aid product fast-tracking.

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