IPC Standard Tolerance Effects
Key Takeaways
How IPC PCB classes are shaped by manufacturing tolerances.
The interplay of yield, reliability, and cost in PCB manufacturing.
Additional points in product design where tolerance adherence is key.
Visual inspection is one of the primary methods of discerning IPC standard tolerances
Manufacturing falls prey to some deviation in translating pixel-perfect features into a physical product. This is to be expected: no matter how cutting-edge the technology is, the operating mechanism for manufacturing equipment can only produce with certainty up to its precision and no further. That said, many devices do not need to be built to the highest manufacturing specifications because the gains in performance do not offset the rise in cost for a particular market price point. For the PCB industry, IPC standard tolerances aid designers and manufacturers by setting minimum acceptability of production processes.
Sample of PCBA Tolerances (Sourced from IPC-A-600 Acceptability Criteria)
Group | Defect/Feature | Class 1 | Class 2 | Class 3 |
| Board edges | Nicks | Nicking does not extend more than 50% of the distance from the edge of the board to the closest conductor or are greater than 2.5mm/~98 mils, whichever is less | ||
| Haloing | Penetration of haloing does not reduce the unaffected distance from the board edge to the closest conductive pattern by more than 50% or more than 2.5mm/~98 mils, whichever is less | |||
| Base material | Voids | Voids do not exceed 0.8mm/~31 mils | ||
| Solder coating | Dewetting | On 15% or less of solderable land areas | On 5% or less of solderable land areas | |
| Holes | Copper plating | Max 3 void/hole. 10% or less of holes have voids. A void is 10% or less of the hole length | Max 1 void/hole. 5% or less of holes have voids. A void is 5% or less of the hole length | None |
| Finishing coat | Max 5 void/hole. 15% or less of holes have voids. A void is 10% or less of the hole length | Max 3 void/hole. 10% or less of holes have voids. A void is 10% or less of the hole length | Max 1 void/hole. 5% or less of holes have voids. A void is 5% or less of the hole length | |
| Contacts | Critical area | Pits, dents, or depressions do not exceed 0.15mm/~6 mils in the longest dimension, with a max of 3 defects per contact, and appears on 30% or less of contacts | ||
| Surface plating gap/overlap | Exposed copper or plating overlap does not exceed 2.5mm/~98 mils | Exposed copper or plating overlap does not exceed 1.25mm/~49 mils | Exposed copper or plating overlap does not exceed 0.8mm/~31 mils | |
| Solder resist | Conductor - conductor registration | Encroachment is only on one side of the land pattern and does not exceed 0.05mm/~2 mils (for a pitch of 1.25mm or more) or 0.025mm/~1 mil (for pitch less than 1.25mm) | ||
| Blistering / delamination | No bridging of connectors | Max 2 per side, 0.25 mm/~10 mils max length in any dimension | ||
| Pattern | Conductor width | Combination of processing or defects can not reduce conductor width by more than 30% | A combination of processing or defects can not reduce conductor width by more than 20% | |
| Conductor spacing | Combination of processing or defects can not reduce conductor spacing by more than 30% | A combination of processing or defects can not reduce conductor spacing by more than 20% | ||
| Planarity | Bow and twist | Bow and twist is no more than 0.75% for assemblies containing surface mount devices, and no more than 1.5% in all other cases | ||
| Dielectric | Laminate voids | Voids no greater than 0.15mm/~6 mils without violating minimum dielectric spacing | Voids no greater than 0.08mm/~3 mils without violating minimum dielectric spacing | |
| Etchback | Between 0.005mm/~0.2 mils and 0.08mm/~3 mils | |||
| Negative etchback | Less than 0.025 mm/~1 mil | Less than 0.013mm/~0.5 mils | ||
| Smear removal | Etchback of no more than 0.025mm/~1 mils | |||
| Metal planes | Unspecified setback is at minimum 0.1mm/~40 mils | |||
| Layer-layer spacing | Unspecified dielectric thickness is at minimum 0.09mm/~3.5 mils | |||
| PTH | Internal annular ring | Hole breakout is allowed provided it does not violate minimum conductor width | Annular ring of at least 0.025mm/~1 mil | |
| Surface pad wicking | Maximum of 125µm / ~4300µin | Maximum of 100µm / ~3900µin | Maximum of 80µm / ~3200µin | |
| Blind/buried via fill | No fill material | At least 60% | ||
| Flex/rigid-flex | Coverlay | In any direction from conductors, separation should be no larger than 0.8mm x 0.8mm/~31 mils x ~31 mils and not within 1mm/~39 mils of the board edge. 3 or less separations within a 25mm x 25mm/~980 mils x ~980 mils area. Separation is no more than 25% of conductor spacing | ||
| Adhesive squeeze-out (land) | At least 240° solderable annular ring for land | At least 270° of 0.05mm/~2 mils solderable annular ring for land | 360° of 0.05mm/~2 mils solderable annular ring for land | |
| Adhesive squeeze-out (foil) | Maximum 0.5mm/~20 mils (foil thickness >70µm) or 0.3mm/~12 mils (foil thickness no greater than 70µm) | Maximum 0.2mm/~8 mils (foil thickness >70µm) or 0.4mm/~16 mils (foil thickness no greater than 70µm) | ||
| Wicking/ migration under cover layer | Discretion of manufacturer and supplier | Extends no more than 0.5mm/~20 mils | Extends no more than 0.3mm/~12 mils | |
| Laminate evaluation | Voids or cracks in a rigid-flex area no greater than 0.15mm/~6 mils | Voids or cracks in rigid material of rigid-flex area no greater than 0.08mm/~3 mils. Voids or cracks in flex material of rigid-flex area no greater than 0.5mm/~20 mils | ||
| Metal core | Core-conductor spacing | Minimum of 0.1mm/~4 mils | ||
| Insulation cracks | Combination of processing or defects shall not reduce the spacing between conductive surfaces below 100µm/~3900µin. The combination of processing or defects shall not exceed 75µm/~3000µin from PTH into hole fill | |||
IPC Classes: Easy as 1, 2, 3
Any mention of IPC quality standards has to touch upon the Class of the board. As shown in the table above, requirements differ between the board Class: tolerance for defects and process variance is overall least demanding for Class 1 and most stringent for Class 3. Not every condition becomes more exacting with increasing Class designation, as some acceptability criteria is a simple binary check regardless of Class for especially egregious manufacturing defects. These Classes are divided among manufacturing difficulty as necessitated by the end products:
Class 1 electronics or general electronics indicate devices that require the most basic criteria for approval. This class of devices is geared towards consumer electronics as well as computers and supporting peripherals. Class 1 devices are generally treated as highly disposable by end users, as technological improvements keep costs low and lead to rapid depreciation. As there is less of an emphasis on the uninterrupted function of the boards, more defects and production errors are permissible to keep yield high.
Class 2 electronics or dedicated service electronics are used in applications where interruptions to service should be minimized. These can include devices and equipment used in communications or business settings where downtime represents a significant loss to users and operators. In terms of manufacturing, Class 2 PCBs require higher inspection and testing discernment, so fewer boards from production runs are accepted.
Class 3 electronics or high-reliability electronics have the strictest production standards, but for good reason: interruption to the service could be an immediate hazard for users, such as in medical or aerospace applications. Whereas downtime should be deterred in Class 2 electronics, it must be absent in Class 3 electronics. Since device reliability is key, Class 3 devices have the highest rejection rate of all IPC Classes, depressing yield and increasing cost.
It’s important to note that the IPC classification covers both bare board and assembly. That is, a bare board that meets Class 3 standards and a subsequent assembly that meets only Class 1 standards would be overall labeled a Class 1 PCBA. Therefore, there is a twofold incentive for manufacturers:
Test before and after processes to eliminate boards that don’t adhere to the targeted IPC Class at the earliest possible point in production to avoid pouring additional resources (labor, materials, energy, time, etc.) into failing boards.
Keep equipment well-maintained and technicians well-trained while verifying process outcomes to ensure downstream manufacturing steps do not negate boards that were passing standards.
At the design level, the layout can use a comprehensive design rule set to maintain compliance with manufacturing technology and the targeted IPC Class.
Maintaining IPC Standard Tolerances Throughout Design
Design rules serve as the go-between for layout and manufacturing, acting to eliminate the inclusion of unproducible features (or features that would significantly increase cost and reduce yield) while maximizing the freedom of the designer. Before beginning the layout, engineering, designers, and manufacturing will want to agree on a set of design rules that embrace a design for manufacturing (DFM) framework. DFM’s first order of business will focus on the stackup for defining conductor width/spacing for targeted impedance values and the thickness of the board for through-hole aspect ratios. The former will rely on powerful field solvers to determine the conductor settings, depending on the surrounding dielectric layers and distance to reference planes, while the board width will set the lower fabricable limit for drill sizes.
Tolerance also creeps up in other areas of the design. Beyond IPC specifications, a board could betray its design intent where the layout fails to follow or convey the information precision set out by the engineers:
Design documents - Make sure that measurements used in the board layout offer the same resolution as those seen in the document. Higher precision may incur greater manufacturing costs, while lower precision will impact true position and overall quality.
Stay on-grid - Especially when contending with a dense assembly, it can be easy to jostle components or features around to make extra room. Performed carelessly, this can move components off-grid. This can put manufacturing at a disadvantage: design rules feature some compensation for manufacturing tolerances, and the true positioning of an off-grid component combined with acceptable deviation due to processes can result in a board that passes rule checks only to fail inspection.
Enhance DFM With Multi-Phase Design Flow Synchronization
Designing with IPC standard tolerance in mind assures manufacturers of the layout quality, minimizing time spent on revisions and restarting production. Many stages of product development may relax DFM principles for several valid reasons, but layout designers will want to be sure that boards set for manufacturing – especially high-volume lots – are designed to the technical limitations of manufacturing. The comprehensive Constraint Manager, just one of Cadence’s PCB Design and Analysis tools, supports users with customizable DFM and is fully integrated with OrCAD PCB Designer (and other Cadence software) for ease of operability.
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