Learn Ethernet PCB Routing to Optimize Circuit Routing Practices

September 16, 2019 Cadence PCB Solutions

Ethernet routing with four cables plugged into it

 

It was supposed to be days before the examinations for the electronics paper, but screams of ‘Epic Kills’ and ‘Godlike’ are drummed into my ears as I was engrossed in the game of DOTA. In the early 2000s, computers shifted to ethernet ports, and that caused gaming to take a major leap into the future.

Today, most of us are connected to the internet via wireless means. However, the ethernet port remains a preference in some applications. Transmission through LAN cable is still considered more reliable and has a higher speed than WiFi. 

How Improper Ethernet Routing Affects Signal Performance

For PCB designers, ethernet routing is a formidable challenge as its high speed means increased susceptibility to interference if routed carelessly. The most common ethernet speed today are 100 Mbps, 1,000 Mbps, and 10Gbps. Even at the lowest rate, you’ll want to muster all your knowledge and tread carefully in design.

An ethernet design that was routed without abiding by any specific rules is an invitation for disaster on the prototype PCB. In some instances, the firmware engineer testing the design would have difficulty establishing a connection on the ethernet port. Less severe, but equally troubling issues is to have unstable connections or limited speed due to signal integrity problems.

Troubleshooting ethernet issues after the PCB has been manufactured and assembled is not easy. It’s better to get the design right during the design stage to prevent costly post-production issues.

Top Considerations For Ethernet Routing

A typical ethernet design consists of the PHY component and the magnetics. The PHY or Ethernet Physical Layer is a component that interfaces link-layer signaling to the ethernet’s physical layer’s analog differential analog signal.

The magnetics, a common term used in ethernet design, helps to isolate the internal circuitry from transient and common mode noise from external LAN cable. The signal traces that run between the magnetics and the PHY are high-speed analog and extremely sensitive to interference. 

But your attention shouldn’t purely be focused on the PHY and magnetics. Most ethernet designs involve an ethernet MAC of a microcontroller that interfaces with the PHY. The interface involved clocked signals that run up to 50 MHz in the RMII protocol or 125 MHz for SMII. You’ll want to pay equal attention to the digital connection between the ethernet MAC and PHY.

 

A picture of a carefully routed circuit board for ethernet capacity

PHY and magnetics must be neither too near nor far.

 

Electromagnetic interference is a real concern in ethernet design as it involves bridging analog and high-speed digital signals. Clocking signal that drives the PHY and common mode noise from the LAN cable can cause interference to the Ethernet signals. Thus, component placement and routing strategies have a significant impact on ethernet routing.

Ethernet PCB Routing Guidelines

When tasked to design electronics that transmit over the ethernet, you’ll want to abide by these guidelines. 

 

1. Place crystal near to the PHY and keep the trace short. 

2. Keep the PHY at least 25 mm away from the magnetics to prevent EMI issues. However, both the PHY and magnetics shouldn’t be too far apart as it attenuates the analog signal.

3. Ensure that the differential pairs between the PHY and magnetics are routed in parallel and free from other high-speed signals.

4. Pull up resistors on the PHY differential pair must be placed within 10 mm from the traces.

5. Place decoupling capacitors close to the power supply pins of PHY. 

6. Ensure a solid ground plane is present beneath the differential signals for the return path. Never route signals over the split plane as that may cause EMI.

7. No via should be present on the analog differential pairs to prevent impedance discontinuities. Keep them on the same plane. 

8. Avoid routing PHY differential pairs near the edge of the PCB to avoid interference coupling from external elements.

9. Link layer signaling between PHY and MAC should be routed in parallel and maintain the same length.

 

Close-up of trace routing on a circuit

Ethernet differential pair signals must be routed in parallel.

 

Designing with ethernet components is a formidable challenge, but using the right PCB design software can minimize the risk of errors. Cadence Allegro PCB Designer helps enable system-level design and analysis, particularly useful in ethernet design applications.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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