Issue link: https://resources.pcb.cadence.com/i/1541046
28. Minimizing Layer Transitions on Critical Nets Every time a signal changes layers (via), it introduces additional parasitic inductance and capacitance, breaks up the return current path, and increases the chance of impedance discontinuities. Multiple layer changes (via "hopping") accumulate delay, degrade signal edges, and can compromise both signal integrity (SI) and electromagnetic compatibility (EMC). For high-speed, timing- critical, or sensitive analog signals, minimizing layer transitions is essential to maintain predictable timing, reduce jitter, and control radiated EMI. When And Where To Apply Apply this tip to all critical nets: high-speed clocks, data buses, differential pairs, precision analog signals, and reset lines, especially those with tight timing or skew budgets. Factor it into your placement and initial routing strategy. An illustration of continuous layer transitions using unnecessary via hopping in OrCAD X PCB Layout 3D