Issue link: https://resources.pcb.cadence.com/i/1541046
28. Minimizing Layer Transitions on Critical Nets How To Implement 1. Strategically place source and destination components: f During placement, align components so that critical nets (e.g., clock, memory bus, SERDES lane) can be routed directly on a single layer, adjacent to a solid reference plane, with no or minimal layer changes. f Plan the stackup so that your main signal layers are adjacent to solid ground for best return path control. 2. Route critical nets with the fewest possible vias: f Avoid unnecessary "via hopping" when making detours or escaping BGA/connector fanouts. f If a via is needed, choose the shortest route possible and co-locate vias for paired/differential nets (P and N vias side by side). 3. Maintain return path continuity: f Whenever a signal changes layers, its return current must also change layers, use a ground stitching via (or a via pair) placed within 1–2 mm of the signal via. f This is especially crucial for differential pairs and controlled-impedance lines. 4. Plan BGA and connector escapes carefully: f For high-pin-count devices, reserve dedicated escape channels to minimize forced via use for critical nets. f If multiple layer transitions are unavoidable, match the number and type of vias used on all lines within a matched group (e.g., DDR DQ, SERDES lanes). 5. Limit vias in high-current and low-impedance paths: f For power delivery and high-current traces, every via adds resistance and heating; use wide traces and multiple vias in parallel, or stay on a single layer when possible. 6. Review with SI and EMC in mind: f Simulate signal quality with each layer transition included; expect up to 0.5-1 nH additional inductance per via. f In EMI-sensitive designs, reducing via count lowers loop area and emissions. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Frequent, unnec- essary via hopping Routinely using vias to "dodge" obstacles or crowded areas, especially on critical nets – Plan routing paths early to minimize via transitions. Missing return path vias Forgetting ground stitching vias near every signal via breaks return continuity and increases EMI – Simulate your design to check for any return path issues. Ignoring via count in matched groups Mismatched delay and skew from different via counts in differential pairs or bus lanes – Keep via count identical across matched nets or pairs. Stackup not planned for critical net routing Placing critical nets on layers that don't allow direct, uninterrupted routes – Define the layer stack early.