Issue link: https://resources.pcb.cadence.com/i/1180280
Embedded Component Design Embedded Component Design October 2019 26 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. the respective placebound shapes where an overlap produces a DRC. The check uses placebound shapes that are appropriate for embedded layers. Summary Understanding parameters and constraints associated with embedded component design. ■ All parameters are located in the bottom section of the Cross-section Editor form. Choose Embedded Layer Setup tab to display options. ■ Parameter numbers 5 and 6 are reserved for Indirect Attach. ■ Constraints are used to check for height violations within the substrate, cavity gap from Placebound and illegal placement of components. ■ Constraint settings are located in Setup – Constraints – Modes – Design –Package. ■ DFA clearance values are sourced from the Top side of the DFA Table by default but you have the option to control by each embedded layer. Embedded Geometry Subclasses The Embedded Geometry supports the following subclasses: ■ ASSEMBLY_EMBEDDED_LAYER ■ DFA_BOUND_EMBEDDED_LAYER ■ DISPLAY_EMBEDDED_LAYER ■ PASTEMASK_EMBEDDED_LAYER ■ PLACE_BOUND_EMBEDDED_LAYER