Cadence PCB Best Practices

Embedded Component Design

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Embedded Component Design Embedded Component Design October 2019 24 Product Version 17.4-2019 © 1999-2019 All Rights Reserved. global parameter value for "Via connect height" will be added to the package height. The "Package Height to Layer" check addresses the possibility that there will be two packages on consecutive embedded layers that have overlapping x-y boundaries. A DRC violation will be created if the packages intersect in the z-direction. The DRC error code is C-H. ■ Edge of Package to Edge of Cavity clearance: Verifies the separation between the edges of a package placebound to edge of cavity outline. The distance can be entered in the Analysis Modes form. If no value is entered, 0 is assumed. The DRC error code is C-S. ■ Illegally Placed Embedded Components: This check runs as part of the legacy package to package DRC check. For example, it flags components with the value of the

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