How Parasitic Capacitance and Inductance Affect Your Signals

Once I started working with sensitive electro-optical components that output weak electrical signals, I started to realize the importance of signal integrity on our signal processing boards. Little did I know that something as simple as trace length or board thickness could produce massive fluctuations in my signals. After many nights staring at datasheets trying to understand the problem, I started to understand how equivalent capacitors and inductors were being formed all over my board.

With lower speed digital, lower frequency analog, or purely DC circuit boards, parasitics are often ignored because they do not have an appreciable impact on the functionality of these devices. Designers of PCBs that operate at high frequency, high data rates, and using mixed signals must take account of parasitic capacitance and inductance during the layout phase.

Parasitic Capacitance and Inductance in Your Board

Parasitic inductance is often taken as an afterthought in high speed design, power electronics, and even multiboard power systems or systems with high-strength wireless capabilities. Any structure of semiconducting or conducting material on a PCB will have some parasitic inductance, leading to problems like crosstalk, induced currents due to EMI, noise coupling, and other effects that degrade signal quality.

Unfortunately, parasitic capacitance and inductance in a PCB are unavoidable. A PCB is composed of a number of parallel conducting elements that are separated by an insulator, basically forming a capacitor. Likewise, conductors on a PCB will inevitably form complete loops, creating an equivalent inductor.

Measuring the parasitic inductance and capacitance in a PCB is extremely difficult. However, it can be calculated directly from first principles. Generally, you’ll find that the parasitic inductance in various places in your board is on the order of nH, while parasitic capacitance reaches on the order of pF. Very large boards with longer and/or wider traces can have much higher parasitic capacitance and inductance.

Managing traces in your printed circuit board can be difficult

Problems in Digital and Analog Circuit Boards

Every pad that appears in your board adds its own parasitic capacitance, and every trace adds its own parasitic inductance. Pads also add their own parasitic resistance that can incur IR losses, although this can be minimized with proper soldering.

When working with any components that switch quickly, especially switching power supplies, the momentary burst of current from the switching component and the propagating signal along a trace will induce a voltage spike in a nearby trace. A trace with a larger parasitic inductance will experience a larger induced voltage spike. This generally increases bit error rates in digital systems, although in power electronics, this can cause involuntary switching in nearby logic circuits.

Parasitic capacitance in power electronics can also slow the switching time in high speed FETs, increasing switching losses. While this mildly reduces the induced voltage spike in downstream components, the strong magnetic fields generated during switching can still cause involuntary switching.

In analog circuits, stray currents induced by high frequency analog signals can interfere with the operation of other analog components, or with the analog portion of a mixed signal component. The analog signal from one trace/component can induce a low level oscillation in another trace/component when the parasitic inductance is as low as 1 nH. Parasitic capacitance also leads to crosstalk, and even low levels of parasitic capacitance can affect the gain of amplifier circuits.

Reducing Parasitic Capacitance and Inductance

Unfortunately, you’ll never be able to completely eliminate parasitics. However, there are some simple layout choices you can make that will help reduce problems from parasitics. Selecting the right components can also prevent signal problems that arise from parasitic capacitance and inductance.

Reducing parasitic inductance requires making the equivalent loop area covered by traces as small as possible. The best way to do this is to place the ground plane for critical traces directly above the layer containing your ground plane. In a 4-layer board, you can place the power plane on the bottom layer and route some sensitive traces between the power and ground planes. This will prevent EMI from signals in one layer from inducing noise in signals in another layer.

Ensure design integrity with smart layout and circuit board planning.

While making layers in your layer stack thinner will decrease the loop area and the parasitic inductance, it will increase parasitic capacitance. Therefore, you need the sweet spot where inductance is minimized and capacitance is maximized. You can calculate this sweet spot by hand, or you can use simulation tools with different layer stacks to determine the right layer thickness. In some cases, layer thickness will be constrained if you are using a board with a large number of layers.

IC manufacturers have been addressing problems associated with parasitics by implementing new architectures. For example, some newer switching ICs arrange FETs in their chips in three dimensions and parallel/antiparallel orientation. This arrangement resembles a differential pair, which nicely suppresses radiated EMI between these circuit elements. This also nearly eliminates parasitic inductance between neighboring circuit elements in the IC, making these components more immune to radiated or external EMI.

In newer high speed digital applications, where multiple data lines can run at 10s of Gbps, parasitic capacitance and inductance can produce impedance mismatch along the signal path. Any mismatch caused by parasitics will produce reflections somewhere on the line, ultimately increasing timing jitter and bit error rates. Impedance should be matched throughout the signal lines that carry high speed data.

Using the right design software will help you implement the best layout choices and reduce problems created by parasitic capacitance and inductance. A design package that includes simulation capabilities can help you identify impedance mismatches that can arise from parasitics. You can also experiment with different layout options that will help you minimize the effects of parasitics on signal integrity.

Thankfully, Cadence is providing the right layout and design software with easily-integrated analysis and simulation tools to ensure your design workflow doesn’t get disrupted and your designs still maintain their integrity when being shipped out for manufacturing.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.