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Constraints in DDR Routing: The Expansive Power of Limits

Aerial view of a road through the limits of a deciduous forest


To ensure a successful design for building anything, one should target for the same design and functional limitations (constraints) that Nature's millions-years-old laboratory has already developed for that same function. For example, utilizing the natural constraints of the brain's neural system to design electronic circuitry.

It is the same with constraints in DDR routing -- these are design guidelines which evolved in response to the natural expressions of electricity that pose challenges for the designer. Designing with these potential signal integrity issues in the forefront of the designer's mind is critical for eliminating static and ensuring high functionality. This is where applying constraints, or design rules, into the DDR routing design comes in handy. 

What are DDRs?

Printed circuit board (PCB) layouts typically use some form of Double-Data Rate (DDR) memory. As the name suggests, DDR memory allows TWO data bit transitions to occur during a single clock cycle, thereby doubling the data capacity during a single cycle. The term, "double data rate" means that it can fetch data on both the up and the down cycles of the timing clock, unlike the previous versions of RAM which only fetched on one clock edge.

Memory devices are often hand-routed to maintain thoughtful control over potential routing issues, such as proper separation between address, data, and control signals associated with the DDRs. 


Example of a circuit board with DDR routing

DDR routing is becoming more and more widespread through electronics design.


By setting certain limiting parameters into your design right at the outset, your chances for high functionality and signal integrity increase. By observing the natural tolerances of the elements of a circuit while designing with parameters that eliminate static and preserve signal coherence, the greater chances of success when your PCB goes into testing. 

Constraints for DDR Routing

The increased speed of DDR memory circuits has rendered the PCB layout more and more complex. Timing and signal integrity are critical at high speeds with large data transfers. Designers therefore employ a prescribed set of "constraints" -- these are limits, guidelines and techniques to be utilized in the DDR routing layout. Constraints in DDR routing can include elements such as delayed timing and matched lengths, and temperature limits imposed by surrounding components.

DDR routing constraints can feel restricting and demanding to the designer, sure, but consider this: some very bright minds ahead of you have created those constraints in DDR routing to make your job easier and your PCB functionally successful the first time.     

Constraints in DDR routing may involve:

  • Operating temperature

  • Trace angles, length, and distance between traces

  • Termination

  • Supply voltages

  • Setup and hold times


What Happens if Constraints in DDR Routing are Ignored?

Failure to follow recommended constraints in DDR routing will produce circuits that do not perform as intended and will function erratically. Difficult to troubleshoot, memory circuits can malfunction so minutely that data corruption can be seen only when particular data streams are passed in and out, or at specific operating temperatures. 


Colorful circuit board with various electronic components

Adhering to design constraints ensures less susceptibility to errors


Designing using suggested constraints in DDR routing is less troublesome than using simulation software to evaluate timings and predict potential electromagnetic interference (EMI). Simulation sometimes requires several iterations to achieve EMI compliance.

The never-ending drive towards miniaturization has increased the incidence of designs where analog, digital, and RF circuits are closely combined with high voltage circuits. These high voltage circuits require additional constraints in DDR routing in the form of increased electrical clearances and isolation for operator safety.

Cadence's Allegro PCB Designer is a scalable design tool that contains everything needed to create a PCB layout with a fully integrated design flow. The heart of Allegro PCB Designer contains a constraint management system, PCB Editor, for creation, management, and validation of constraints in DDR routing. It also includes an auto-interactive router, and interfaces for mechanical and manufacturing CAD programs. 

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts