Addressing Coupling Capacitance in Designs

August 11, 2020 Cadence PCB Solutions

Key Takeaways

  • Parasitic coupling between different nets occurs through parasitic inductance and capacitance.

  • Coupling capacitance defines how easily signals can transfer between nets to produce a return path, crosstalk, or overall circuit impedance.

  • Front-end design features in your circuit simulator can help you examine how the coupling capacitance in your nets will influence signal behavior.

A densely routed printed circuit board with coupling capacitance

A complex group of interconnects like these will be influenced by coupling capacitance.

Whether you’re designing circuits for a new IC or for a PCB layout with discrete components, coupling capacitance will exist between groups of conductors in your design. You can never truly eliminate parasitics like DC resistance, copper roughness, mutual inductance, and mutual capacitance. However, with the right design choices, you can reduce these effects to the point that they do not cause excess crosstalk or signal distortion.

Coupling inductance is quite easy to spot as it arises in two principle ways:

  • Two nets that are not running perpendicular and are referenced back to a ground plane can have loops that face each other (mutual inductance).

  • Every plane that provides a return current path will have some coupling inductance with its reference nets (self-inductance).

Coupling capacitance can be more difficult to pinpoint as it occurs everywhere. Anytime conductors are placed in a PCB or IC layout, they will have some capacitance. A potential difference between these two conductors causes them to charge and discharge like a typical capacitor. This causes displacement currents to divert away from load components and signals to crossover between nets at high frequency (i.e., crosstalk).

With the right set of circuit simulator tools, you can model how coupling capacitance in an LTI circuit affects signal behavior in the time domain and frequency domain. Once you design your layout, you can extract the coupling capacitance from impedance and propagation delay measurements. By comparing the results, you can determine if any layout changes are required to prevent unwanted signal coupling between nets.

What Causes Coupling Capacitance in a Circuit?

A circuit diagram does not explicitly account for any coupling capacitance between conductors in a circuit. This is because coupling capacitance depends on the following aspects:

  • Geometry. The distance between conductors, their cross-sectional area, and the size of the regions facing each other in the layout will determine the capacitance of the circuit. 

  • Dielectric constant. The dielectric that separates conductors has a high dielectric constant, and the coupling capacitance is directly proportional to the dielectric constant. 

  • Coupling between parasitics. A single conductor can have coupling capacitance with multiple nets. These capacitances combine with other parasitic capacitances and inductances to produce complex coupling, which may be a complicated function of frequency.

Because coupling can be a complex function of frequency, return paths and crosstalk signals may produce results that also differ in frequency from the source signal. This is due to the transfer function of the equivalent network formed by the designed circuit, coupling capacitance, and any other parasitics (DC resistance and parasitic inductance).

Examining how parasitics affect your board requires pre-layout and post-layout simulation tools. Pre-layout simulations are much more flexible, but they don’t account for geometry in your layout as the layout hasn’t been created yet. In contrast, the right set of numerical post-layout simulation tools will account for parasitics almost exactly, but it’s difficult to pinpoint the exact part of the layout that creates the strongest coupling. In addition, you can’t sweep through different coupling capacitance or inductance values to find acceptable parasitic coupling levels without making changes to the layout.

Tools for Modeling Coupling Capacitance

Because the coupling capacitance in your layout is unknown until the layout is completed, the place to start modeling coupling capacitance is in your schematic. This is done by adding a capacitor at strategic locations to model specific coupling effects in your components. This allows phenomenological modeling of coupling capacitance depending on where the capacitor is placed:

  • Input/output capacitance. The input and output pins in a real circuit (ICs) will have some capacitance due to separation between the pin and the ground plane. These capacitance values are usually ~10 pF for small SMD components. This is one of the primary points to be examined in a pre-layout simulation.

  • Capacitance between nets. Placing a capacitor between two nets that carry input signals will model crosstalk between the nets. By visualizing the victim and aggressor net, you can see how switching on the aggressor induces a signal on the victim. Because these capacitances are quite small and crosstalk also depends on mutual inductance, crosstalk simulations are normally only performed post-layout for the highest accuracy.

  • Trace capacitance back to a ground plane. Even if a trace is short, it will still have parasitic capacitance with respect to the ground plane, which is responsible for resonance on short transmission lines.

Example: Coupling Capacitance at a BJT Input Pin

As an example, let’s look at coupling between the input pin of a BJT transistor and its reference plane using transient analysis in PSpice. The schematic below shows an example circuit that includes modeling of the parasitics on a short transmission line. The inductor and capacitor on the short line (L1 and C1, respectively), as well as the resistor, simulate short transmission line behavior with some resistance on the output. The source in this system is a pulsed source ranging from 0 to 5 V with 2 ns rise/fall times and 100 ns repetition rate (10 MHz). The transistor Q1 is a 40237 NPN transistor.

Capacitor C2 is placed to model the pi capacitance at the input to Q1. A more accurate model would include the pin-package inductance connected to the base but we’ll focus on coupling capacitance back to the ground plane for the moment.

Parasitic coupling capacitance in PSpice schematic

Coupling capacitance simulation schematic in PSpice.

To examine how the input coupling capacitance will affect signal behavior and possibly lead to distortion, the value of the capacitor is defined as a global parameter CAP2. This is defined by opening the component properties dialog and setting the component value to {CAP2}. A global parameter needs to be placed on the schematic using the PARAMS part in the Place Part menu in PSpice. In the image below, I’ve defined a parametric sweep range from 10 to 110 pF for C2 (20 pF increments). This gives a total of 6 curves, one for each value of C2. 

Coupling capacitance range in PSpice parametric sweep

Defining parametric sweep ranges in PSpice.

Now that the coupling capacitance range is defined, it’s time to run the simulation and examine how the coupling capacitance affects signal behavior.

Time-Domain and Frequency-Domain Results

The graph below shows a zoomed-in view of the voltage at the emitter for the first pulse in the 10 MHz pulse stream. We can see significant ringing due to resonance on this short transmission line. Ringing is largest when the coupling capacitance is small (green curve, C2 = 10 pF), but the ringing gets smaller as the coupling capacitance increases (purple curve, C2 = 110 pF).

Coupling capacitance and time-domain simulation results in PSpice

Parametric sweep results in the time domain.

The function of coupling capacitance is to shunt high-frequency components in the signal bandwidth to the ground plane as a displacement current. This can be seen nicely in the frequency-domain results, which are calculated with a Fourier transform.

Coupling capacitance and frequency-domain simulation results in PSpice

Parametric sweep results in the frequency domain.

At the high-frequency end of the signal bandwidth (~120 MHz and higher), the peak levels for these frequencies are lower when the coupling capacitance is larger. In effect, Q1 and C2 act like a low pass filter with high cutoff frequency. Note that the knee frequency for these signals, which accounts for ~75% of the total signal power, is at ~175 MHz. We can see that the coupling capacitance starts to cause filtration below this frequency, leading to signal distortion.

Adding Source Impedance Matching

Although there is a slight reduction in ringing as the coupling capacitance increases, newer ICs tend to have smaller features giving smaller coupling capacitance. This is problematic in this case as the transient response leads to an undamped oscillation with a larger amplitude. This highlights the need for source termination in this circuit design. If we match the source’s output impedance to ~50 Ohms, one would expect the transient response to have lower amplitude and, potentially, exhibit a critically damped or overdamped oscillation.

The graph below shows transient analysis results with a 50 Ohm resistor in series with the pulsed voltage source (V1) to provide source termination. This significantly damps the oscillation on the rising edge and makes the transient response critically damped. On the falling edge, there is still some undershoot.

Coupling capacitance and time-domain simulation results with source termination in PSpice

Parametric sweep results in the time domain with source termination.

According to the circuit theory for transmission lines, the source termination resistance that will produce critical damping is double the input impedance of the (line + load circuit) network. The exact resistor required for termination will depend on the value of the coupling capacitance. From a design standpoint, you should try to find a source resistor that can accommodate a range of possible coupling capacitance values in your layout in order to help suppress overshoot/undershoot due to the transient response in this circuit.

Other spots where coupling capacitance may be prominent in this design include:

  • The output from the pulse driver (to ground).

  • The output from the transistor (to ground).

  • Between the transistor output and power pins.

The first two points above combine to increase the capacitance of the interconnect, which slightly reduces its impedance. In terms of the circuit theory, this brings the transient response closer to critically damped or deeper into overdamped, just as was the case with increasing the transistor’s input capacitance. On long transmission lines, the load impedance needs to be considered separate from the line impedance, and we need to look at circuit reflections to determine signal behavior due to coupling capacitance.

Use Post-Layout Simulation to Extract Coupling Capacitance

The parametric analysis tools in PSpice make these types of pre-layout simulations easy. You can analyze how changes in any component or property value affect signal behavior in the time and frequency domains. Once you’ve completed your layout, your post-layout signal integrity tools can help you examine how parasitic capacitance in your layout affects signal behavior and net impedance. You won’t always be examining parasitic capacitance directly. Rather, you’ll want to simulate signal behavior (reflections, impedance, propagation delay, return path, and crosstalk) directly from your layout.

If you like, you can calculate a coupling capacitance value from your impedance results (parasitic capacitance to ground) or from your crosstalk simulation results (parasitic capacitance and inductance to the nearest net). The best signal integrity tools will display these results within your simulation results, giving you a look into coupling coefficients between nets in your layout. This is the type of functionality you’ll find in Sigrity SI Extraction, which provides the values of parasitics directly from post-layout simulation data. You can also examine signal behavior directly with Sigrity Advanced SI, which allows coupling, reflections, impedance, and return paths to be simulated in your layout.

If you’re looking to learn more about how Cadence has the solution for you, talk to us and our team of experts.

 

About the Author

Cadence PCB solutions is a complete front to back design tool to enable fast and efficient product creation. Cadence enables users accurately shorten design cycles to hand off to manufacturing through modern, IPC-2581 industry standard.

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