While the Printed Circuit Board is composed of sheets of dielectric and conductor layers, it’s the vias that really bring a circuit to life and keep it going. Allowing the signals to pass from one layer to another makes this a three dimensional puzzle that can scale to a staggering number of layers.
You don’t have to go back that many decades to find a time when we called them printed wiring boards. The components were mounted to what looks like a peg-board, rows of evenly spaced holes where the leads of the part would extend through two or more of the holes. Then you’d just add wire.
As far as routing consistency, every board was a one-off built up a wire at a time. Government agencies can be given credit for driving the PCB technology towards higher reliability. Along the way the “industrial complex” responded with the following electronics innovations:
- Moving from individual transistors to integrated circuits using dual in-line package (DIP) technology
- Axial and/or radial leaded passive through-hole components gave way to surface mount types with and without leads
- Quad Flat Pack (QFP) and similar devices came along with a full perimeter of signal pins plus a ground slug taking the central area inside the single ring of pins
- Ball Grid Array (BGA) package types that feature a partial or full field of pins
Each of these general categories describe a watershed advancement in device packaging as we went from one transistor to billions of them. The PCB industry responded by going to multiple layers of etch which protected the more vulnerable circuits and allowed for higher circuit density.
Figure 1. Image Credit: Author - A typical mix of components found on a board that features through-hole vias.
The component manufacturers continually outdo themselves in terms of adding functions while reducing size. The end game is a “Marketing Breakthrough” where the company can compare its chip set to the others and claim to take up the least amount of PCB real estate. While that claim may be technically true, the part where the fan-out is left to the designer is the unspoken cost of chip scale packaging.
The Standard Plated Through-Hole Via
Taking a step back from the leading edge, the plated through-hole via still has a long runway. There are plenty of devices where the pitch of the pins will support through vias in the go-to size of 8 mil drill with 18 mil capture pads on all layers. This is the usual size for class 2 commercial applications and allows up to 90 degrees of the drilled/plated hole to break out from the 18 mil pad. Thicker boards will want larger holes as the fab shop doesn’t want to deal with plating high aspect ratio holes. The common .062 inch board thickness is in the sweet spot.
As an aside, I’m going to continue using mils for drill/pad sizes and metric units for device pitches. The two systems are blended in the real world where there are CAM operators and SI/PI people, maybe others, who use mils and they set the rules. Meanwhile the chip makers have settled into decreasing the pin pitch from one rounded metric number to another. I could call it 127 microns or 5 mils. The point is that you want to be comfortable with the common units of measure. Now, where was I?
Class III Design Rules for High Reliability
Going to the high reliability side of the spectrum we will still use the 8 mil drill but with a 23 mil pad on the outer layer and 21 inner layer. These numbers are meant to ensure that there is a minimum of a 2 mil annular ring of metal around the hole on every layer. This has to account for layer-to-layer registration along with hole location and size tolerance.
The vias described above are useful for routing DIP and QFP packages along with the roomy BGA devices where the pin pitch equals or exceeds 0.8 mm. We do have to be careful about managing the vias in the thermal pad that makes up the heart of the QFN/QFP package types. You might get away with adding a few regular vias between the paste stencil openings and calling it good.
When the device is consuming a considerable amount of current, then more vias will have to be placed in the thermal pad. The vias may be filled with a nonconductive material and capped with metal plating so that solder cannot migrate down the holes. Lastly, a conductive fill with little globs of copper mixed with strands of silver in an epoxy base will be the plan for drawing out some serious heat.
Case Study: Thermally Conductive Fill
The end of a fiber optic cable has a transponder that converts the light waves from the glass into electrical waves for copper and also generates the light waves going the other direction using a laser. These photo detectors and lasers get very warm as the units strobe along at 10 to 400 gigabytes per second.
The mechanical engineer thought he had an answer that used a slot in the board and a pedestal in the housing to pass through the board and contact the bottom of the device. He didn’t want to believe that the PCB could not have a plus/minus one mil thickness tolerance. It was a one millimeter board so the standard tolerance would be +/- 4 mils. That didn’t help his pedestal plan but it’s always good when the fab shop confirms your statements.
They tried everything, thermal pad, grease, different heat sinks. There was only one configuration that had a measurable difference. It was the one where I changed the ground holes in the center pad from 10 mils to 13 and had them filled with the expensive two-step thermal epoxy fill. The measurable difference was that it met the spec and we could ship products to Cisco.
General Purpose Printed Circuit Boards Will Continue to use Plated Through-Hole Vias
Plated through-hole vias will be sufficient to fan out BGA packages with lower pin-count and generous pin-to-pin spacing of 0.8 millimeters or more. It may be possible to use PTH vias on a 0.65 mm pitch BGA though it will use a 16 mil capture pad. There is a likelihood that you will hear from the fabricator if you go this way even if you decrease the finished hole size to six mils.
Figure 2. Image Credit: Author - A fan-out scheme for the FPGA shown in Figure 1.
You’ll need to use the one millimeter or even 1.27 mm pitch devices to pull off a high-reliability (class 3) fan-out. The number of layers required grows quickly as each via blocks the routing channel on every layer. We’re lucky if we can get two traces between the vias. Necking down traces to fit the geometry may not sit well with those signal integrity folks.
Rounding Out the Plated Through-Hole Via Discussion
Thankfully, there are FPGA and ASIC vendors who still deal in packages that can be used with a ten to twelve-layer board with through-hole technology. Back drilling may be required for the thicker boards. Extra thin traces and spaces may be required in especially dense areas to allow the signals to escape from the inner part of the BGA devices.
In cases where the vias are incorporated with a heat sink pin, plugging and capping will prevent solder migration while vias filled with thermally conductive material can dissipate a lot of energy.
Figure 3 - Image Credit: Author - Opening up the soldermask for the vias provides a convenient method of attaching a jumper wire.
A row of large vias can be placed along the edge of a board and cut off right down the middle for what’s called a castellated via. The ground net or even various signals can wrap around the edge or even a slot somewhere within the board using castellated vias.
Other than components specifically targeted towards mobile applications, there are still a lot of possibilities to build a PCB using through-hole technology. Power consumption may be higher while edge rates are lower than their miniaturized counterparts. Some of these more robust parts may only be available in the high-temperature version.
If these things are not a concern, then perhaps the basic PCB technology can be used for your simpler projects in a way that extends the expected lifespan. You just have to hope that they keep on building those components.
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