Will Your Microvias Survive? The Physics of Stacking, Aspect Ratios, and Copper Balance in HDI

A lot of engineers stack micro vias two or three layers deep to break out a dense BGA without ever really knowing whether those structures are going to survive the fabrication process. The design looks correct, the clearances are legal, and DRC passes but the board fails in the field. This video covers two completely separate reliability problems that standard design rule checks will never surface, and how to catch both of them before your fabrication files go out the door. The first is via aspect ratio. For laser drilled microvias, the industry standard maximum is 0.75 to 1 meaning your dielectric thickness has to be less than 0.75 times the drill diameter. Violate that and the plating chemistry can't reach the bottom of the hole uniformly, leaving voids in the copper that look fine on the outside but crack under thermal cycling over time. The exact number you need comes from your fabricator's process capabilities, not your software defaults that distinction matters more than most designers realize. Beyond aspect ratio, the choice between stacked and staggered microvias carries real manufacturing cost and reliability consequences that catch people off guard. Stacking is sometimes unavoidable in a dense BGA escape space simply doesn't allow an offset but stacked vias require the lower via to be copper filled and planarized before the upper laser drill can land on it. That's two extra process steps, added cost, a new opportunity for fill voids, and a stress concentration point every time the board goes through a thermal cycle. There's also a known bad structure that shows up more often than it should: a micro via stacked directly on a mechanical buried via. Allegro X PCB Layout will flag that as an error if your constraints are set up correctly, but only if you've actually defined the stack up properly in the first place. The second problem has nothing to do with vias at all it's copper distribution. HDI boards go through multiple lamination cycles, and each time layers are pressed together under heat and pressure, copper and dielectric expand and contract at different rates. If the copper distribution isn't symmetrical from the top of the stack to the bottom, the board bows when it cools because the coefficient of thermal expansion mismatch is pulling unevenly. Those in the know put the threshold at roughly 10 to 15% mismatch between corresponding layer pairs before warp risk becomes serious and a warping board means your tight micro via tolerances, and potentially your components, are in trouble during reflow. The Allegro X Film Area Report gives you copper percentage per layer before your files go to fab, and if you do find an imbalance, copper thieving adding dummy fills in sparse regions is the fix. We walk through both checks on a real Nvidia Jetson AGX Orin carrier board, which is about as good a real-world reference as you can get for how these principles look in a production HDI design.