This Stream includes all of the HDI Via Design (Mar/April) players
A lot of engineers stack micro vias two or three layers deep to break out a dense BGA without ever really knowing whether those structures are going to survive the fabrication process. The design look
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That's what this video is about. At high frequencies anything above a few hundred megahertz, which includes DDR5, PCIe Gen 5, and USB the return current doesn't spread across the ground plane looking
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Standard DRCs won’t flag power delivery failures that may be present in your HDI PCB. When you break out a dense BGA, every microvia introduces an anti-pad into your power and ground planes. For a 0.4
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Designing an HDI PCB for AI accelerator applications? Signal integrity alone isn't enough. If your microvias can't deliver the power, your design is set up to fail. In this video, we walk through a tw
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Learn to configure HDI via rules in Allegro X. Explore spacing constraints, stacked microvia limits, copper spacing, and alignment to ensure manufacturable, reliable designs for high-speed HDI PCBs.
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Learn BGA escape routing strategies for HDI PCB designs. Discover fanout, via-in-pad, and layer transitions in Allegro X to optimize signal integrity, manufacturability, and performance.
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Learn how via selection impacts HDI and high-speed PCB designs. Explore microvias, blind, and buried vias for signal integrity, EMI, and manufacturability in Allegro X.
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High-speed HDI designs operating around 1 GHz and beyond often run into signal integrity, EMI, and impedance control issues that don’t originate in routing, they originate in the stackup. When return
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