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IC Design Steps: Keeping Pace with Modern DFM

Key Takeaways

  • Why IC design requires an approach from two different directions.

  • A look into the process of preparing IC design files.

  • Cost and yield concerns constrain the physical design of the IC.

Overlapping silicon wafers top-down view

Dense transistor count silicon wafers start with a series of IC design steps.

Despite its relatively recent introduction, the transistor is the most produced item in human history. Barring a completely unforeseen technological breakthrough, this is unlikely to change: device transistor counts have increased exponentially over the decades since its introduction, and the miniaturized manufacturing miracle is at the heart of the digital revolution. However, the trend of increasing transistor counts is pushing the limits of design and manufacturing processes. IC design steps build an iterative process that marries a focus on details with a high-level, systematic inclusion of device features and functionality.

Iteration and Bidirectional Design Motivations

IC design steps are similar to PCB design, but differences arise due to more constraints and tighter tolerances. Very-large-scale integration (VLSI) guides IC design, combining billions of MOSFETs into a single chip for dense electronic functionality like system-on-chip (SoC). Also similar to PCB design, the VLSI design flow is an iterative process, with the caveat that iterations during physical manufacturing are magnitudes more expensive than a small run of prototypes. Unlike PCB design, however, chips lack user serviceability after fabrication – it is a binary pass/failure product.

The iterative nature of IC design descends from a combination of top-down and bottom-up design styles:

  • A top-down design is decompositional in a reverse engineering sense. Design teams formulate a greater system overview and add detail to sub-systems during the design process.
  • A bottom-up design builds up individual processes before incorporating them into the system. 

While the bulk of IC design focuses on the bottom-up method, as it allows the most granular details to shape the higher levels of design sophistication, a top-down approach can assist in leveraging bottom-up design to improve performance outcomes. For example, size is one of the two premier design constraints for ICs, and implementing the top-down design of the architecture without an accurate estimation of the chip area is likely to exceed the allotted space. 

Instead, IC design should integrate the physical constraints at the earliest possible time to build out device functionality with complementary features. The best designs synthesize the intricacies of bottom-up and the oversight of top-down methodologies:

  • Conceptual design - The specifications of the IC. As with all engineering, IC properties will have reasonable tradeoffs to match design intent. However, the IC layout will permit significant freedom within these constraints, allowing designers to select the most suitable topology and placement.

  • Schematic design and simulation - The components of the IC need interconnect definition. The netlist must fully describe connections to power, ground, and external I/O pins. To properly implement the schematic, design teams must create symbols representing component groupings known as circuit modules. In addition to the layout, these modules are also integral for the simulation stage of the design. The simulation stage is twofold: a design validation and an opportunity to optimize performance.

  • Layout and verification - Layout can either enhance or inhibit critical performance areas, primarily the power, size, and speed of the IC. Additionally, careful placement will negate contributions to parasitic resistance and capacitance. The layout will then perform a design rule check (DRC) using configurable DFM constraints to detect conflicts between the proposed circuit and manufacturing requirements.

  • Post-layout simulation - This stage will be a refined version of the schematic-level simulation after ascertaining that no discrepancies exist between the layout and schematic. It is a more robust simulation that accurately models real-world performance with parasitics and signal delay parameters folded into evaluations. The post-simulation results offer feedback on the layout, and matching the design specifications may necessitate further revisions.

The Minutiae of Physical IC Design Steps

There remains a significant gap between a completed design and a manufactured IC. Fabrication tools and techniques will demand adherence to minimum feature size and spacing rules. Manufacturability assurance will depend both upon iterations and the quality of prior IC design steps:

  • Floorplanning - Placing billions of individual transistors would be infeasible; instead, transistors are partitioned within functional blocks, which are then recursively defined into smaller sub-blocks. The floorplan must best group these blocks to minimize area and facilitate routing. 

  • Placement - This phase concerns the exact positioning of the blocks on the chip. The first placement will be a rough arrangement of the cells before an evaluation step that aims to optimize space while complying with design restrictions. An estimation of the routing space guides whether the placement requires continued iteration.

  • Routing - The space between the blocks reserves space for the interconnects, with the connection process spanning two phases. Routing must preserve space and minimize the effects of parasitics by occupying the shortest path possible between pins. First, global routing organizes connections in alternating preferred directions across the metal layers. Detailed routing follows, which specifies the geometries of these connections.

  • Extraction - The physical layout translates into a netlist for the most accurate level of simulation that incorporates precise details. A final check of electrical parameters is necessary to establish signal delay and timing.

Step Through IC Design with Cadence Solutions

IC design steps require exacting levels of control and precision to incorporate the dense transistor fabrications in modern packages. However, IC design does not conceptually depart far from the processes found in PCB design, which shouldn’t be surprising as the latter was an emulation of the latter’s manufacturing practices. Boards or components require sophisticated toolsets with state-of-the-art modeling to continually achieve performance at the margins of design. Cadence’s PCB Design and Analysis Software suite offers electronic development teams expansive and modular simulation capabilities. Simulation results can then seamlessly integrate into OrCAD PCB Designer for a fast and full-featured design environment.

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