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Very-Large-Scale Integration

Key Takeaways

  • The benefits of shrinking transistor sizes on total electrical performance.

  • Further methods of IC integration for special use cases.

  • Bottom-level design techniques to optimize wafer layout.

 View of transistor layout on a silicon wafer

Very-large-scale integration is paramount to maximizing wafer layout efficiency.

IC product engineering is extremely demanding, and unlike PCB design where prototyping can be used as a guide for design revisions, the high cost of materials and processing for ICs means design teams need to succeed on the first production run to avoid incurring significant losses.

The current period of very-large-scale integration (VLSI) represents an era of incredible gains in performance. ICs have become more powerful, smaller, and less expensive, with better power consumption on a per-transistor basis. Small form factor devices like wearables and portables would simply be unrealizable with their current feature set if not for improvements in IC manufacturing technology. 

A Comparison of IC Generations

Transistor count (per chip)

Process node

IC sophistication

Proof of concept

Small-scale integration (SSI)

1 - 100




Medium-scale integration (MSI)

100 - 1,000




Large-scale integration

1,000 - 100,000




Very-large-scale integration

100,000+ (modern day: 10,000,00+)

100,000+ (modern day: 10,000,00+)

RAM, processors


The Motivation for Very-Large-Scale Integration

As demand for new devices and novel revisions of existing products increases, manufacturing technology must also grow to meet the need. On the other side of the coin, improvements in manufacturing allow for innovation in design that were previously unrealizable. The shrinking of the transistor also has multiple performance benefits.

Performance Benefits of Small Transistors

  • Quadratic reduction in the area due to a linear dimension reduction.
  • Reduces capacitance linearly (capacitance for a physical device relates plate area over plate separation).
  • Voltage reduces linearly (an electric field is a voltage over field length).
  • Current reduces linearly (for both electrostatic and electrodynamic cases) due to its relationship to voltage.
  • Delay decreases linearly (with some slight variation possible due to dielectric constant differences) according to the speed of light in a non-vacuum.
  • As the reciprocal of time delay, frequency increases reciprocally.
  • Switching power decreases quadratically (due to the presence of the square voltage term in the calculation).

This collection of factors is known as Dennard scaling, and while it has been upended by physical realities much like Moore’s Law, it’s easy to see why for decades it was the guiding principle for IC optimization. An unfortunate downside of transistor shrinkage is an increased susceptibility to electrostatic discharge due to smaller air gaps and length of features.

Manufacturing technology has become specialized from VLSI in certain cases. While the overall goal remains the same (reducing transistor size and space, increasing performance), the method differs.

IC Integration Formats

Wafer-scale integration (WSI)

The standard planar process of IC manufacturing uses a standard cell that is repeated across the semiconductor wafer while allocating space for packaging. WSI instead utilizes the entire wafer as a single package, allowing designers to recoup additional space that would be lost to sub-dividing the wafer. Because of the size and cost of the wafer-level component, this technique is reserved for intensive applications where space for assembly is not a concern.

System-on-chip (SoC)

A level of abstraction above an IC, SoC incorporates all the functionality of a system (for example, a computer) into a single die. While this greatly increases manufacturing costs, there are commensurate reductions in power consumption, heat generation, transmission delay, and equivalent size.

Three-dimensional IC (3D-IC)

Like a congested city, IC designers have sidestepped space restrictions by building vertically. This can be seen currently with stacked ICs: similar to a PCB, dies are arranged and connected vertically using vias and wire bonding to provide greater returns on functionality and performance per land pattern. On the other hand, monolithic 3D ICs, which are constructed in three dimensions on a single die, remain an ongoing area of research.

It is worth noting that some industry usage defines an additional generation of IC development known as ultra-large-scale integration (ULSI) following VLSI, but others see this as an unnecessary distinction.

VLSI Design Best Practices for Layout

IC design begins with a design hierarchy akin to that of a PCB. From the highest to the lowest level of abstraction, design follows a standard workflow:

VLSI Design Best Practices for Layout

CMOS Technology Offers the Best of Both Worlds

While all steps of the design process are touched by VLSI, it is the latter two steps (known collectively as bottom-level design) where the talents of IC designers are most called upon. In a series of physical and chemical processes, designers layer insulators and conductors in such a fashion to form the switches that define modern semiconductor production. 

Complimentary metal-oxide semiconductors (CMOS) are the most common semiconductor due to their excellent power performance and are comprised of an n-channel and p-channel metal-oxide-semiconductor field effect transistor (MOSFET). N-channel MOSFETs and p-channel MOSFETs (nMOS and pMOS, respectively) differ in their charge carrier (electron for n-channel, holes for p-channel), which affects the construction of the FET. 

For either type of FET, designers can capitalize on available space by placing gates over shared doped regions (nMOS) or shared doped-well regions (pMOS). Metal then connects the wells of the individual FETs as well as the paired nMOS and pMOS for power, ground, and input/output for the universal gates.

Maximizing IC Gate Placement

With a general idea of how to build ICs, layout guidelines take over. These rulesets provide minimum settings that reflect the precision of the production equipment and allow for the slight variance inherent to manufacturing. As conserving space is the name of the game, below are a few points to keep in mind.

IC Layout Guidelines

Gate orientation

A vertical orientation is best suited when pMOS and nMOS are of similar sizes and have multi-input datapaths. Horizontal gates work better when there are size mismatches between pMOS and nMOS FETs.

Combined doped regions

A continuous doped region that spans multiple pMOS or nMOS FETs minimizes gaps and allows for denser placement.

Euler’s Rule

Designers can simplify the layout of a particular gate array by tracing identical gate paths for the pMOS and nMOS FETs.

Tip the Scales in Electronic Design With Cadence Solutions

Very-large-scale integration and other IC production methods focus on drawing the best electrical and thermal performance out of an extremely limited area. As demand for smaller and more powerful devices continues to push manufacturing capabilities to current limits, continuing  research looks for new production techniques to continue the torrid pace of innovation from the past several decades. 

Within the current mode of production, however, designers need cutting-edge toolsets with extensive functionality to support dense layouts and product requirements. For the system level, Cadence’s PCB Design and Analysis software suite provides a multitude of features for modern HDI designs, while the Integrity 3D-IC Platform offers designers a fast and powerful environment for quick turns for even the most complex projects.

Leading electronics providers rely on Cadence products to optimize power, space, and energy needs for a wide variety of market applications. To learn more about our innovative solutions, talk to our team of experts or subscribe to our YouTube channel.