A couple of weeks ago it was time for the 18th International Conference and Exhibition on Device Packaging (or IMAPS for short, although those are the initials of the organizer, the International Microelectronics Assembly and Packaging Society). Advanced packaging was all over the technology news again that same week when Apple announced the M1 Ultra, which consists of two M1 Max chips joined by what they called an interposer but other people would call an interconnect bridge. An interposer is generally understood to be something bigger than the die that go on top of it, whereas a bridge is small and only underlays the edges of the die where the connections are. For more details, see my post March 2022 Update: Intel Video, India, Apple.
At the IMAPS conference, Cadence's John Park presented 3D Packaging versus 3D Integration.
He started by pointing out that people get to system-in-package (SiP) from two different directions. Taking components on a PCB and moving them to a multi-chip module is the first. The second is doing the sort of integration that might have been done on a big SoC a few years ago, but instead moving the die into an advanced package. There is probably a much longer list of things that make chiplets attractive, but here are a few of the big ones:
- Flexibility in picking the best process node for the part. In particular, SerDes I/O and analog does not need to be on the "core" process node
- Better yield due to small die size
- Shorten IC design cycle and integration complexity by using pre-existing chiplets
- Lower manufacturing costs by purchasing known-good-die (KGD)
- Volume manufacturing cost advantage when the same chiplet(s) are used in many designs
One thing that has changed from the IC-focus of advanced packaging are the flows. On the left in the diagram above the flows are PCB-like. On the right, the flows are IC-like. Integrating lots of different technologies, heterogeneous integration, pulls together all the technologies that have been used over the years. In particular, advanced packaging and advanced integration—approaches such as wafer-on-wafer and bumpless integration.
We can think of packaging-based 3D as "backend 3D" and advanced integration as "frontend 3D". Backend 3D is micro-bumped with timing signoff for each die separately, and with I/O buffers on each die. There is typically no concurrent design of the dies. This has been a common approach for memory and CMOS image sensor for years. For frontend 3D the die are typically bonded directly (copper to copper, or similar). There are no I/O buffers between the die, meaning that concurrent design and analysis is mandatory, with timing-driven routing and static timing signoff required (for digital designs). There is potential placement in the Z-axis when multiple dies are stacked on top of each other, meaning that a given block might be assigned to a different die as the design progresses.
This is the next paradigm shift in packaging, the next step on the path to true 3D IC design with lots of die stacked on top of each other so that signal distances are short. Of course, there are thermal issues that need to be analyzed and managed, since a die on top of another die can act as an insulating blanket or a heatsink, depending on the details.
There are still challenges to making this ecosystem a reality, ranging from the availability of assembly design kits (ADKs) to common standards for die-to-die (d2d) interconnect, to full support in EDA tools. For more on these last two issues, see my posts:
- Universal Chiplet Interconnect Express (UCIe)
- Introducing the Integrity 3D-IC Platform for Multi-Chiplet Design
One challenge to creating tools to support these manufacturing flows is that designs can get very large, literally over 100B transistors, perhaps in multiple technologies. This generates a requirement for a high-capacity, multi-domain, multi-technology database to underlie the tools that do the work. Only this way can we have a high-capacity common 3D-IC platform.
Another area where we will have to wait and see what happens is how chiplets are sold. To date, most chiplets (apart from memory) have been designed as part of a single system or set of systems. In the longer term, it is possible that bare die will be available in just the same way as packaged parts are today. Going beyond that, it is possible that distributors (or new companies) will market and sell die from a variety of manufacturers as they do today with packaged parts. With communication between chiplets becoming standardized, this is more of a business challenge than a technical challenge, or at least it soon will be.
Read John Park's White Paper 3D-IC Design Challenges and Requirements (registration required).