Issue link: https://resources.pcb.cadence.com/i/1541046
4. Validating Symbol-to-Footprint Mapping How To Implement 1. Gather authoritative sources: f Download the latest part datasheet, package drawing, and recommended land pattern (often in IPC-7351 format). f For complex ICs (BGAs, QFNs, connectors), obtain manufactur- er-provided CAD files or STEP/3D models when available. 2. Pinout and mapping check: f Cross-verify every pin number and signal name in the schematic symbol with the manufacturer's datasheet's pinout table. f For ICs, confirm pin 1 location/orientation, power/ground pins, and any not-connected (NC) or "do not use" pins. f For connectors, check both the PCB side and the mating side, ensuring the orientation and numbering match your enclosure or harness. 3. Footprint and land pattern check: f Measure pad pitch, pad size, and outline in your EDA tool against the datasheet's recommended land pattern. f Check mechanical dimensions: courtyard (keep-out) outline, overall package size, and pin 1/polarity indicator. f Review solder mask and paste mask layers, verify mask openings are present for all pads, and that paste windows match manufacturer guidance for thermal pads or large leads. f If using via-in-pad (QFN, BGA), confirm via tenting/filling matches assembly requirements. 4. 3D model and height check: f Attach or import the manufacturer's 3D model for collision/height clearance analysis (especially for tall connectors, heatsinks, relays, or shield cans). f Use the 3D viewer to verify that the component doesn't collide with mechanical features, other parts, or the enclosure. 5. Footprint preview and library validation: f Use the tool's footprint preview function to compare symbol pins, pads, and pin one marks directly in layout. f Check that the pad numbering in the footprint matches the logical pin numbers from the symbol. 6. Special considerations: f For BGAs: Double-check ball grid orientation (dot/chamfer), array size, escape fanout, and the recommended via strategy. f For polarized parts (diodes, tantalum caps, LEDs): Confirm polarity marks on both the silkscreen and copper layers. f For connectors: Ensure mounting holes and shroud keepouts match the mating part and case openings. 7. Document and sign off: f For each custom or critical footprint, save a validation note (with screenshots or markups) in your project folder or as comments and attachments as part of revision control. f If working in a team, peer-review any new or modified library parts before approving for use. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Trusting third-party or auto-generated libraries Many "standard" libraries contain invalid pin swaps, bad outline sizes, or missing paste/mask — Always verify against the actual datasheet. Forgetting about mechanical interference Overhanging pins, tall bodies, or shrouds may collide with neighbors or the enclosure — Enable 3D clearance checks and place keepouts for height/edge constraints. Pin 1 or orientation errors Swapped orientation leads to total circuit failure —Double-check the footprint's pin 1 indicator matches both the datasheet and the symbol.