Issue link: https://resources.pcb.cadence.com/i/1541046
35. Performing Design Rule Checks (DRC) and Electrical Rule Checks (ERC) Iteratively How To Implement 1. Define all necessary design and electrical rules at project start: f Include rules for trace width/spacing, via size and pad clearances, copper-to-edge, component-to-component spacing, minimum annular ring, power/ground constraints, and net class-specific rules (e.g., high-speed, analog, HV). f For ERC, specify rules for unconnected nets, input/output conflicts, short circuits, and floating pins. 2. Configure your CAD tool for real-time or batch DRC/ERC: f Enable online DRC (interactive checking) if available, so violations are flagged as soon as they occur. f Set up ERC to check for schematic-level errors; open pins, multiple outputs tied together, incorrect power connections, etc. 3. Run checks at every major design step: f After schematic entry, run ERC to catch netlist and logic errors. f After placement, run DRC for footprint, spacing, and courtyard violations. f After each routing phase, run DRC for trace/pad spacing, plane violations, and via checks. f After adding copper pours or making netlist changes, re-run both DRC and ERC. 4. Review and resolve violations as they appear: f Don't just "waive" or ignore violations unless fully justified and documented. f Track recurring issues, update design rules, or placement practices to prevent repeat errors. f If a violation cannot be immediately resolved, flag it for follow-up and document the rationale. 5. Perform a full DRC/ERC before generating Gerbers, IPC- 2581, ODB++, or manufacturing files: f Ensure zero showstoppers, address or formally waive all critical and major errors. f Document all rule settings, waivers, and fixes for manufacturing and review. 6. Engage in peer review or automated audits: f Have another engineer or a design review tool audit the DRC/ERC report before final signoff. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Running DRC/ERC only at the end Creates a flood of errors that are time-consuming and costly to resolve – Run incremental DRC/ ERC checks throughout the design process. Ignoring "minor" violations Even small spacing or connection errors can cause assembly or test failures – Flag for follow-up. Mismatched or outdated rules Not updating rules to reflect current fab or component capabilities can miss critical errors – Update your design-rule libraries to match current fabrication capabilities and component datasheets. Lack of documen- tation on waived errors Leads to confusion and risk during manufacturing and debug – Maintain a clear record of all waived errors in design notes.