Issue link: https://resources.pcb.cadence.com/i/1541046
3. Finalizing the PCB Stackup Early How To Implement 1. Consult your fabricator and requirements: f Request your fab's "standard stackup tables" or their stackup planning tool. f Collect requirements for impedance-controlled nets (e.g., USB, DDR, LVDS, Ethernet) and for power/ground separation, isolation, or high-voltage domains. f Decide on target board thickness (e.g., 1.6 mm/62 mil is common) and max copper weights (usually 1 oz/ft² for signal, 2 oz for high current/power planes). 2. Choose the number and order of layers: f For basic digital or analog boards, 2 or 4 layers is often sufficient. For high-speed or complex systems, 6+ layers are typical. f Example: ɢ 4-layer: L1 (Top Signal), L2 (GND), L3 (PWR), L4 (Bottom Signal) ɢ 6-layer: L1 (Signal), L2 (GND), L3 (Signal), L4 (PWR), L5 (GND), L6 (Signal) 3. Assign functions to each layer: f Place signal layers adjacent to solid reference planes (GND or PWR) for clean return paths and strong field containment. f Pair power planes with ground (e.g., L3 PWR next to L2 GND) for low-in- ductance decoupling. f Avoid sandwiching two signal layers together without an adjacent plane. This increases crosstalk. 4. Specify dielectric thicknesses and materials: f Standard prepreg/core thicknesses are often 0.13 mm (5 mil), 0.18 mm (7 mil), or 0.2 mm (8 mil). f Low-loss laminates (e.g., FR408HR, Isola, Megtron) may be needed for high-speed/RF. f Use these values in your impedance calculator for accurate width/spacing rules. 5. Determine trace widths and controlled impedance: f Use an online calculator or your CAD tool's field solver to determine the required trace width and spacing for 50 Ω single-ended and 90–100 Ω differ- ential pairs, for each layer (these values will differ with copper thickness and dielectric). f Example: On a 1.6 mm, 4-layer stack with 1 oz outer/0.5 oz inner copper, 50 Ω microstrip may require 8–10 mil traces, while 100 Ω differential may need eight mil width/8 mil spacing. 6. Lock in via styles and drill details: f Confirm allowed via types with your fab (through-hole, blind, buried, microvia, via-in-pad). f For high-density BGAs, microvias (0.1-0.15 mm laser-drilled) may be needed. f Record finished hole sizes and padstack details for every via in your rules. 7. Document and import into your design tool: f Enter the confirmed stackup, layer names, copper weights, thicknesses, and materials into the CAD tool's stackup/cross-section manager. f Assign signal/plane types to each layer and verify that all rule-driven features reference the correct layers. 8. Communicate and review: f Share the stackup (diagram and table) with your team, SI/PI engineer, and contract manufacturer (CM) before routing. f Note stackup details (materials, thicknesses, controlled-impedance specs, via types) in your fabrication drawing for build and review. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Guessing the stackup or using old defaults Results in traces that can't meet impedance or power targets — Work with your fab early on to define your stackup and define target impedances and tolerances before placement/routing. Not aligning trace widths/spacing to stackup Mismatched impedance on critical nets can cause SI/EMI failures – Create net classes for critical signals and enforce them as DRC rules so routers and pours follow them automatically. Overlooking via types or limitations May force a re-spin if the fab can't build what's designed – Confirm which via types your fab supports and verify cost. Neglecting documentation Missing or unclear layer stackup information is a major source of CAM questions, build errors, and test failures – Provide complete fab drawings: layer stackup table with materials/thicknesses, copper weights, impedance tables with targets/tolerances, via notes, etc.