Issue link: https://resources.pcb.cadence.com/i/1541046
31. Isolating Clocks, Resets, and Sensitive References from Noise Sources How to Implement 1. Physically separate noise-sensitive nets from aggressors: f Place clock generators, oscillators, and reference sources away from high-current switching nodes, SMPS inductors, digital buses, and power FETs. f Route clock and reference lines with the shortest, most direct paths - avoid proximity to switching power or high-speed digital nets. f For resets, use pull-up or pull-down resistors close to the IC pins to stabilize the line. 2. Provide dedicated ground and shielding: f Place clocks and analog references over solid ground planes, avoid crossing splits or regions with heavy return current from digital or power blocks. f Use ground guard traces (well-stitching vias) on both sides of especially sensitive lines, connecting these shields to the main ground. 3. Minimize coupling through power rails: f Decouple analog and digital power rails as close as possible to the ICs, using local LDOs or ferrite beads where appropriate. f For analog references, use high-quality bypass caps (e.g., 1 µF + 0.1 µF, X7R) directly adjacent to the pin. 4. Avoid crossing domains and layer changes: f Do not route clocks or references over plane splits or transitions between ground domains (AGND/DGND). f When changing layers is necessary, provide a nearby ground via to maintain return path continuity. 5. Implement a good probe/test point strategy: f Place test points for clocks, resets, and references only at endpoints (not mid-trace) and use high-impedance probes during bring-up to avoid loading or picking up noise. 6. Verify during bring-up: f On the prototype, check for noise/jitter on clocks and references using an oscilloscope or spectrum analyzer. f Validate that resets are stable, with no false triggers on power-up or during switching events. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Routing clocks parallel to or above noisy traces or power planes Increases coupled noise and jitter – Route perpendicular where crossing is unavoidable. Crossing plane splits Breaks up the return current and increases EMI pickup – Add stitching vias to provide a low-impedance return path. Sharing reference rails between analog and digital Enables digital noise injection into precision analog or clock domains – Tie reference rails at a single point. Leaving resets floating or inadequately pulled Risks false or unstable operation – Use appropriate pull-up/pull-down resistors where necessary.