Issue link: https://resources.pcb.cadence.com/i/1541046
30. Treating Length and Skew Matching as Numeric Constraints How To Implement 1. Calculate propagation delay for your stackup: f Use your stackup's dielectric constant (Dk) and layer geometry to determine the speed of signal travel - typically 140-180 ps/inch (5.5-7.0 ps/mm) for FR-4, microstrip, or stripline. f This allows you to convert timing requirements (e.g., max 20 ps skew) into a physical length budget (e.g., ≤0.15 inch or 3.8 mm). 2. Define length/ skew constraints in your CAD tool: f Assign constraint groups: e.g., DDR DQ[0:7], DQS, DQM, address/command buses, or SERDES pairs. f Set maximum allowed skew (e.g., intra-pair ≤5 mil, byte-lane to DQS ≤25 mil, per interface spec) and, if needed, target lengths for delay matching across groups. 3. Use dedicated routing rules and layer assignments: f Route all members of a match group on the same layer to minimize variation in propagation delay. f Avoid unnecessary vias or layer changes; if they are required, match the number and type across the group. 4. Implement length tuning (serpentine) as needed: f Use length-tuning features ("accordion" or "serpentine" traces) to add controlled length where needed. f Place tuning segments over solid ground and away from noisy or high-crosstalk areas; distribute evenly to avoid localized impedance changes. f Match length by actual propagation delay (not just physical length) if different layers are involved. 5. Continuously verify during routing and review: f Use your PCB layout tool's length-matching and skew-checking reports to monitor compliance as you route. f After routing, review all timing groups for max/min/ average delay and adjust as needed. 6. Cross-check with SI/PI simulation: f For critical interfaces, simulate timing and eye diagram performance using actual routed lengths and propagation data. f Update constraints and reroute if simulations show marginal timing. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Guessing or eyeballing lengths Leads to out-of-spec skew, especially with non-rectilinear layouts or unequal via counts – Measure using length matching or phase tuning features to meet timing specifications. Ignoring delay differences between layers Even equal physical lengths on different layers can yield different delays – Account for propagation delay between layers. Forgetting to match via count and type Unmatched vias add delay and jitter – Keep via count, drill size, and pad type identical in differential pairs. Clustering all tuning in one spot Causes local impedance disconti- nuity and may introduce reflection points – Spread serpentine or accordion tuning sections along the route.