Issue link: https://resources.pcb.cadence.com/i/1541046
26. Routing Differential Pairs with Consistent Geometry and Return Paths How To Implement 1. Define differential pair rules and constraints: f Set up design rules for differential pair width and spacing to achieve the required differential impedance (usually 85-100 Ω; consult interface specs and your stackup's field-solver). f Set maximum allowed length mismatch (skew) between positive (P) and negative (N) lines, often ≤5-10 mil (0.13-0.25 mm) for most high-speed standards. 2. Route as tightly coupled, symmetrical pairs: f Keep P and N traces side-by-side, with the same width and the same reference plane underneath throughout their length. f Maintain uniform spacing between the pair, avoid S-shaped jogs, unintentional spread, or inconsistent gaps. 3. Minimize length and via mismatches: f Ensure both traces of the pair are the same length within your constraint, use meanders only when needed, and place them in the same physical area to avoid picking up different noise. f If vias are required, make sure both P and N transition layers are at the same location, using matched via types and lengths. 4. Avoid stubs and branches: f Route each pair point-to-point between driver and receiver; never "tee off" or create branches. f Place test points at the endpoints or use purpose-designed probe fixtures that don't add significant stubs. 5. Ensure return path continuity: f Differential signals return their current not just through each other, but also via the reference plane underneath. f When changing layers, ensure a solid ground plane is present and use stitching vias near the signal vias to allow the return current to follow closely. 6. Stay away from plane splits and noisy areas: f Never route differential pairs across ground or power plane splits; this interrupts the return path and can cause severe signal degradation. f Keep pairs away from noisy aggressors, such as switching power nodes or large digital buses. 7. Validate with simulation or measurement: f Use your PCB layout tool's differential pair length, skew, and impedance checking tools to confirm compliance. f In prototypes, check eye diagrams and bit error rates with appropriate test equipment. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Routing P and N traces separately around obstacles This creates a length mismatch and destroys noise immunity – Ensure that the nets are defined as differential pairs in the constraint manager. Letting pair spacing or reference plane change uninten- tionally Results in impedance mismatches and increased EMI – Maintain constant spacing. Layer changes without return path planning Induces mode conversion and crosstalk – Provide stitching vias or nearby ground connections to ensure a continuous return path. Using the same rules for all interfaces Different standards have specific impedance and skew requirements – Review each inter- face's specifications and apply tailored design rules.