Issue link: https://resources.pcb.cadence.com/i/1541046
23. Managing Split Planes and Power Islands Correctly How To Implement 1. Determine if plane splits are necessary: f Only split ground planes if required by the IC vendor or system architecture (e.g., to isolate noisy digital from sensitive analog). f Use power islands for separate voltage domains (e.g., 3.3V, 1.8V, AVDD, DVDD), keeping each with its own well-defined copper region or plane. 2. Map signal and return paths: f For each net that crosses a split, ensure a return path exists; preferably by routing over a solid, continuous plane. f Never route high-speed, clock, or sensitive analog traces over plane splits; return current will detour, increasing loop area, EMI, and SI errors. 3. Bridge split planes at a controlled star point: f For analog/digital ground splits, connect at a single "star point," ideally under or next to the key IC (e.g., ADC, codec), as specified by the IC vendor. f Use a zero-ohm resistor, bead, or dedicated trace - do not rely on stray copper or accidental shorts. 4. Avoid fragmenting planes with unnecessary cuts or voids: f Ensure plane splits are deliberate, well-documented, and follow system-level isolation needs. f Avoid anti-pads or clearance voids that accidentally create unintended islands or break up return paths. 5. Connect decoupling and bypass caps to their local planes/islands: f Decouple each domain locally. Do not connect analog decoupling to digital planes, or vice versa. f For multi-rail designs, keep each island's decoupling and filtering self-contained. 6. Check for unintended islands or isolated copper: f After the copper pour, review with the PCB layout tool's net inspector for "dead copper" or isolated islands that are not tied to their net or main plane. 7. Simulate and validate: f Use SI/PI or EMI simulation to ensure plane splits do not degrade performance. f Validate with measurement during prototype bring-up, checking for ground bounce, voltage drops, or noise coupling. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Routing critical nets over splits Causes massive SI/EMI problems and returns current detours – Try to route critical signals over continuous planes only to ensure return path isn't inter- rupted. Floating or unconnected copper islands Acts as antennas or introduces unpre- dictable voltages – Remove any unused copper/islands as you update shapes. Bridging at multiple points Creates ground loops and undermines isolation – Define a single, controlled connection point between domains. Forgetting local decoupling for each island Risks unstable supplies and noise issues – Place decoupling capacitors close to each power island or IC.