Issue link: https://resources.pcb.cadence.com/i/1541046
21. Pouring Copper with Electrical Intent, Not Just for Fill How to Implement 1. Assign a clear electrical net to every pour: f Each copper pour should be explicitly tied to a net (e.g., GND, VCC, AGND, shield). Never leave a pour floating. f Set pour connectivity style: "solid" (continuous) for power/ ground, "thermal relief" for pads to allow reliable soldering, or "no connection" for keepout zones. 2. Stitch pours to the main plane frequently: f For ground pours, connect to the main ground plane or net with vias every 5-10 mm (2-5 mm for RF or high-speed areas). f Stitch around board edges, under BGAs, and anywhere high-current or high-frequency return paths are needed. 3. Remove copper "islands" and slivers: f Use the EDA tool's options to automatically delete islands and thin slivers (e.g., <10 mil or <0.25 mm wide). f Isolated copper islands can act as unwanted antennas and should be avoided for EMC. 4. Manage pour proximity to signals: f For sensitive analog, high-speed, or impedance-controlled lines, keep pours at a calculated distance or use guard pours (closely spaced ground pour) with dense stitching to minimize crosstalk and noise pickup. f Avoid tying analog ground pours directly to digital grounds except at a single star point, if required by system architecture. 5. Maximize thermal benefit where needed: f For heat-producing parts (regulators, FETs, LEDs), connect copper pours directly to thermal pads and out to large copper areas. f Use multiple vias to tie top and bottom pours together for effective heat spreading. 6. Check for unintentional isolation: f Verify that all intended pads and traces are actually connected to the pour. Small errors here can create open circuits. 7. Review and simulate for EMI and SI: f Use simulation or pre-compliance EMC tools to evaluate if copper pours improve or worsen EMI. f Check for unintended resonant cavities or "patch antenna" effects in large unbroken pours. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Floating pours with no net assignment Acts as antennas or capacitively couples noise – Run a DRC to flag any unconnected copper pours in your design. Sparse or missing stitching vias Reduces effectiveness for EMC and increases ground bounce – Place vias to serve a purpose like tying ground planes together, supporting high-speed signals, and manage thermal paths. Leaving small islands or slivers Results in unpredictable EMC perfor- mance and risk of unintended shorts – Set up DFM constraints to flag unwanted fragments of copper. Connecting analog and digital grounds every- where Destroys the intended isolation and creates ground loops – Use a solid ground plane with a single controlled AGND-DGND tie point.