Issue link: https://resources.pcb.cadence.com/i/1541046
10. Planning BGA and Fine-Pitch Fanout Before Surrounding Placement How To Implement 1. Study the manufacturer's package and land pattern: f Download the full package drawing and "recommended fanout" from the datasheet or manufacturer's app notes. f Identify ball or lead pitch (e.g., 0.65 mm, 0.8 mm, 1.0 mm for BGAs) and body size; count rows/columns. 2. Choose an escape strategy based on pitch and layer count: f For pitches ≥0.8 mm, through-hole (mechanically drilled) vias can often be used for outer rows. f For 0.5-0.65 mm pitch, microvias (laser-drilled, often 0.1-0.15 mm diameter) or via-in-pad are usually required. f For ultra-fine pitch (≤0.5 mm), sequential buildup or via-in-pad with filled/capped vias is standard. 3. Reserve fanout channels before placing neighboring parts: f Leave open "escape corridors" for each row/column to reach the inner signal layers. f Block out areas around the package in your layout as no-go zones for other component footprints or tall parts. f Place decoupling caps as close as possible to power/ground balls, ideally on the same side for best performance. 4. Assign signal, power, and ground balls to appropriate layers: f Plan signal, power, and ground assignments with escape in mind - dedicate nearby planes for GND and PWR under the BGA to minimize via count and support return currents. f For memory interfaces or high-speed I/O, ensure direct escape to low-noise reference planes and keep length-matched groups in mind. 5. Plan and implement the fanout pattern in your CAD tool: f Use the fanout generator (if available) to create via arrays or stub traces for each ball. f For BGAs, fan out the outermost rows first; inner rows may require stacked or staggered microvias and additional signal layers. f Apply design rules for minimum trace width/spacing, via size, anti-pad clearance, and soldermask tenting. 6. Check for manufacturability and rework: f Confirm that all via types and dimensions are within your fabricator's capabilities and yield targets. f Leave a clear zone around the BGA/QFN for X-ray inspection, rework nozzles, and thermal cycling. 7. Lock fanout and surrounding placement: f Only after fanout and escape planning are validated should you begin placing surrounding components, support passives, and starting general routing. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Placing adjacent parts before fanout Results in blocked escape paths and trapped pins – Create compo- nent-free zones and perform a fanout study. Mismatched via or pad sizes to fab capabilities Causes low yield, open circuits, or assembly problems – Request your fab partner's current design rules document for via/pad sizes. Overcrowding decoupling or tall parts near BGAs Blocks rework tools and increases defect risk – Optimize component placement by floorplanning and establish a keepout zone. Underestimating layer count Fine-pitch BGAs often require extra layers for full pin access – Analyze component density such as pin count and size