Issue link: https://resources.pcb.cadence.com/i/1541046
5. Using Descriptive Net and Component Naming How To Implement 1. Establish naming conventions: f Use industry-standard prefixes: U (ICs), R (resistors), C (capacitors), D (diodes/LEDs), Q (transistors), L (inductors), J (connectors), TP (test points), Y (crystals/oscillators), F (fuses), SW (switches), etc. f For hierarchical or modular designs, consider adding block numbers (e.g., U10x for all ICs in block 1 - some design tools automatically support this). f Document these conventions in your project's style guide and/or as part of your corporate standards. 2. Descriptive net naming: f Name nets by function and voltage: VDD_3V3, VDD_5V0, GND_ ANA, USB_DP, UART_TX, ADC_IN1, CLK_100MHZ, RESET_N, EN_ GATE, etc. f Use consistent prefixes for buses or arrays: DDR_DQ[0..15], I2C_ SCL, I2C_SDA, SPI_MISO, SPI_MOSI. f For differential pairs, use _P/_N suffixes or a common prefix: USB_ DM/USB_DP, ETH_RXP/ETH_RXN. 3. Assign and manage reference designators: f Group passives (C, R) near their parent IC (e.g., C101 and R102 for decoupling and pullup around U1). f Keep designator sequences logical and contiguous to aid BOM creation and assembly troubleshooting. 4. Apply naming in the CAD tool: f Assign or edit net names in the schematic editor; do not leave default auto-generated net labels on important signals. f In your layout tool, ensure the netlist imports all custom names correctly; check that no net gets renamed or lost during the process. 5. Use names for rule binding and review: f Apply length/impedance constraints to nets or net classes by name for high-speed interfaces (e.g., "Apply 100 Ω diff rule to all nets with 'USB' prefix"). f Use clear names to identify test points and debug hooks in bring-up and production test scripts. 6. Documentation and output: f Make sure all net and component names appear in the schematic, netlist, and layout outputs. Provide a signal legend in your design documentation. f During review, cross-check net names between schematic, layout, and simulation models for consistency. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Leaving default or cryptic names Net00045, Res_16, or arbitrary numbers makes later edits and reviews error-prone — Use clear, descriptive, and searchable names. Inconsistent naming Using multiple conventions or renaming nets in different domains leads to confusion and bad constraint assignment — Create a naming convention document to ensure the same name is used across domains. Failing to update names in all tools Some EDA flows require explicit sync of net/ component names between schematic and PCB — Check the import log for missing or renamed items.