Issue link: https://resources.pcb.cadence.com/i/1541046
34. Specifying Controlled Impedance and Reference Plane Requirements How To Implement 1. Identify all controlled impedance nets and interfaces: f Mark all nets (single-ended and differential) requiring specific impedance in your schematic and layout tool. f Typical values: 50 Ω (single-ended), 90–100 Ω (differ- ential), but always check protocol and silicon requirements. 2. Work with your fabricator on stackup and impedance modeling: f Provide a list of required impedances and target tolerances. f Use field solvers or the fabricator's modeling tools to set trace width, spacing, and dielectric thickness for each impedance. f Confirm copper weights, layer order, and material Dk (dielectric constant) are consistent with modeling. 3. Document impedance requirements clearly: f Include a stackup drawing with all controlled impedance layers, trace widths, and spacing. f List all critical nets, their required impedance, and reference planes in fabrication notes. f Specify that impedance test coupons must be included for fab validation. 4. Route all controlled impedance nets over continuous reference planes: f Ensure there is a solid ground (or power) plane directly beneath the signal layer for the entire net length. f Avoid crossing plane splits, voids, or changes in the reference layer. 5. Enforce impedance-driven routing rules in the CAD tool: f Use constraint manager or net classes to assign required widths, spacing, and layers for each impedance-controlled net or group. f Set up DRCs to flag violations automatically during layout. 6. Validate with simulation and measurement: f For critical signals, simulate impedance and signal quality (SI) in your tool. f On prototypes, request and review impedance coupon measurements to verify as-built compliance. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Omitting impedance modeling and stackup validation Can result in out-of-spec signals and unreliable operation – Integrate SI simulation into your design flow. Routing over split or absent reference planes Causes impedance discontinuity and SI/EMC failures – Use DRCs to flag traces crossing split planes. Not documenting impedance needs in fab notes May result in the fab using default or incorrect stackup/process – Include explicit impedance targets, stackup details, and layer assignment in fab notes. Using only width/ spacing rules without checking actual impedance Manufacturing variations require careful modeling and validation – Use SI simulations and field solvers to verify impedance.