Issue link: https://resources.pcb.cadence.com/i/1541046
33. Optimizing Decoupling and Bulk Capacitor Placement How To Implement 1. Select the right types and values for each role: f Use high-frequency ceramic capacitors (e.g., 0.01-0.1 µF, X7R) closest to the IC power pins to suppress high-fre- quency noise. f Add mid-value ceramics (e.g., 1-4.7 µF) for broader spectrum filtering. f Place large-value bulk capacitors (e.g., 10-100 µF tantalum, aluminum, or polymer) near power entry points, regulators, or high-current loads to handle large transients and low-frequency dips. 2. Minimize distance to IC power and ground pins: f Place each decoupling cap on the same side of the board as its IC, as close as possible (preferably within 1-2 mm trace length). f Connect directly to power and ground pins with thick, short traces or planes; avoid long loops, narrow traces, or unnecessary vias. 3. Use multiple vias for grounding and current return: f For high-speed, high-current, or multi-layer boards, connect cap grounds to the plane with multiple vias - especially for bulk and bypass caps serving fast logic. 4. Spread caps along the power path: f Distribute decoupling caps across the board, especially near clusters of logic, memory, or analog/RF blocks. Do not cluster all caps at the voltage regulator or at a single corner. 5. Validate effective ESR and resonance coverage: f Use combinations of different values and package sizes to ensure low effective series resistance (ESR) and broad frequency response. f Avoid using only identical value caps, as this can cause unwanted resonance "holes" in the filtering spectrum. 6. Place bulk caps for inrush and board-level stability: f Near power connectors or regulators, use large caps to absorb startup surges or supply dips from sudden load changes. f For battery or hot-pluggable systems, add bulk capacitance to minimize voltage droop during connector mate. 7. Review with power integrity simulation or oscilloscope: f Simulate or measure supply noise at the IC pin under maximum switching or load conditions. Adjust values and placement if noise exceeds spec. Common Pitfalls, Their Impact, and How to Avoid Them Common Pitfall How to Avoid it Placing decoupling caps far from IC pins Excess trace inductance severely degrades effectiveness – Use DRCs to flag capacitors that are placed beyond a maximum allowed distance. Undersizing bulk caps or missing them entirely Can cause voltage dips or oscilla- tions during startup or load transients – Maintain a checklist for each power rail and verify placement during review. Using only one value/ cap type Risks incomplete coverage and resonance "holes" – Set a multi- value decoupling strategy. Long, thin traces to caps Increase impedance and reduce decoupling performance – Set guidelines for maximum trace length and minimum width.